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fpga mandelbrot fractal generator

It is verilog implementation of mandelbrot fractal generator. Code tested on Artix-7 XC7A35T FPGA board.

mishamisha
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hardware
FPGA artix-7 mandelbrtot fractal VGA mig7

This project was created on 10/13/2020 and last updated 4 years ago.

Description

*For vga frame buffer used onboard ddr3 256MB ram with xilinx mig7 memory controller
*Used double buffering for low latency
*Fractal size and vga resolution is 1024 X 768
*Fractal frame is generated one time untill next zoom
*Max iteration for fractal generation is 500

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Dan Maloney wrote 10/14/2020 at 18:27 • point

The Mandelbrot set always fascinated me. Nice to see it implemented on a FPGA like this. Thanks for sharing!

  Are you sure? yes | no

misha wrote 10/15/2020 at 09:41 • point

Thanks Dan

  Are you sure? yes | no

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