1. Address area and switches

The operation panel has been simplified to realize the first concept, and the toggle switches for address setting are 10 bits. So, the memory space is only 1 kbytes. I thought that I could still execute a simple machine language program. Zero page is $ 000 - $ 0FF, stack area is $ 100 - $ 1FF, vector area is converted $FFFA - $FFFF to $3FA - $3FF and the rest are free areas.

2. Address LEDs

The LEDs for address display are also 10 bits, and the status of the address bus is always displayed. In the case of single step operation, the execution address of the instruction is displayed in sequence. Without this function, it is difficult to debug because you cannot see the runaway instruction in single step operation.

3. Data switches and LEDs

The data setting switches are 8 bits. The LEDs on the data bus display the data value of the memory for which the address is set when the CPU is stopped. If you operate the write switch at this time, the status of the data setting switch is written to the memory. When the RUN/HALT switch is set to the RUN side, the CPU goes  from a halt state to normal continuous execution.

4. Circuit

The external interface has an 8-bit parallel write port and a read port. The power supply is a four 1.2 V NiMH AA rechargeable batteries or an external 5 V power supply. The LSIs mounted on the board are R6502A for CPU and HM6116LP-3 for SRAM. Thirteen standard CMOS logic ICs configure a clock generator, 8-bit parallel port, address decoding, and Direct Memory Access(DMA) bus control as shown in the schematic to realize the second concept.

5. Circuit operation

The CPU halt state is performed by setting the ready(RDY) signal to low state with the switch S21. And the single instruction operation is performed by setting the RDY signal to high state until the SYNC signal becomes high state by pushing the switch S22. In the halt state, the CPU IC1 continues to output the execution address to the address bus, so the address LEDs D2-D11 display the execution address. The address bus of the memory IC2 is disconnected from CPU by the 3state buffer IC4 and the Address switches S2-S11 are enabled. When write switch S1 is operated, data switches S12-S19 are connected to the memory IC2 though 3state buffer IC7, and write enable signal is applied to the memory. 

    The RDY signal is set to high state during the CPU reset by the resistor R54. Otherwise, in my case the R6502A had not result in complete correct address progression in subsequent single-step operations. I have confirmed in my testing of four PERSEUS-7s and multiple individual CPU chips that there is a probability that. In this computer it is assumed a user operation that the CPU is in the halt state at power-on and that the program is executed in a single step without ever entering the RUN state. Therefore, I thought that it was important to take countermeasures against this problem. It seems that this control is not necessary for the R65C02. With this circuit, The R6502A and the R65C02 have the same number of dummy steps until the first program instruction is executed in a single step operation after CPU reset.

6. Making 

18 cm x 12 cm x 5 cm aluminum die-cast housing was used to realize the third concept.  It was processed with a hand drill and files. Wiring on the universal board was done by wire wrapping. The switches and LEDs are mounted on the panel of the housing and connected to the main board with two 26p flat cables. First, I made one prototype. Then I made 3 more of the same ones by hand. The making time per unit is about 60 hours. So, including the operation test, it took a total of 4 months.

7. Results

I was able to make a small portable stand-alone 6502 machine language computer. Memory writing with DMA and single instruction operation worked fine. If it was a machine language program of several tens of bytes, I...