A few things now in progress.

A more stable vhdl code for the memory map. It still retains it's multicomp roots, but is now more suited to 24bit addresses and 16-bit data used by the 68000. This will allow me to create a better design for the bios and bootstrap.

n_basRom1CS <= '0' when cpu_uds = '0' and cpuAddress(23 downto 20) = "1110" else '1'; --E00000-E0FFFF
n_basRom2CS <= '0' when cpu_lds = '0' and cpuAddress(23 downto 20) = "1110" else '1';       

hiMem <= '1' when cpuAddress(23 downto 20) = "1111" else '0';
hiMemRegAddr <= cpuAddress(7 downto 0);

spiMem  <= '1' when hiMem = '1' and cpuAddress(19 downto 16) = x"4" and hiMemRegAddr(7 downto 4) /= x"4"  else '0';  --f4
ethMem  <= '1' when hiMem = '1' and cpuAddress(19 downto 16) = x"4" and hiMemRegAddr(7 downto 4) = x"4" else '0';  --f4
timerCS  <= '1' when hiMem = '1' and cpuAddress(19 downto 16) = x"3" and hiMemRegAddr(7 downto 4) = x"3" else '0'; -- timer f3003
rtcCS <= '1' when hiMem = '1' and cpuAddress(19 downto 16) = x"3" and hiMemRegAddr(7 downto 4) = x"4" else '0';  -- f3004
fpuMem  <= '1' when hiMem = '1' and cpuAddress(19 downto 16) = x"5" else '0'; --f5 
ioMem  <= '1' when hiMem = '1' and cpuAddress(19 downto 16) = x"2" else '0';  --f2
uartMem  <= '1' when hiMem = '1' and cpuAddress(19 downto 16) = "0000" else '0'; --f0


-- ____________________________________________________________________________________
-- RAM
ram_cen <= '0' when  cpuAddress(23 downto 20)  < X"E" and n_reset = '1' else '1';

I've also now started working on a physical adapter for the Arty pmod boards which will convert from 3.3v to an 8-bit 5v bus. I will use the RC2014 bus design as it seems to have a lot of pre-built modules. At the moment I am thinking that the vhdl code will translate the 68000 bus signals to the RC2014 Z80 style so the add-on boards can be used without modification. Level shifting bus transceivers will manage the i/o and I will probably add 2mb of fast sram for the main system to use as well.