A work in progress 68008 card for RC2014 and BP80 busses
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68008-rc2014-v3.pdfSnapshot of the schematicAdobe Portable Document Format - 67.03 kB - 08/18/2021 at 20:38 |
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I think you need to ensure the !WR pulse ends before asserting !DATACK. The classic way to do this is to have !DS control a 74LS164 shift register. See this circuit:
https://cdn.hackaday.io/files/295311263454304/J061_cct.png
There is a full explanation of how it works in the manual. You should be able to generate the timing you want very easily.
https://hackaday.io/project/29531-stebus-io-prototyping-board
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The memory card is able to respond within the first cycle. So according to several other board designs (and of course the famous newsletter) - dtack can be grounded.