Diagram1.png

Gate driver timing diagram for 4%, 25% and 98% duty. Stars mark possible cross conduction or risk of overlap.

Portable Network Graphics (PNG) - 43.56 kB - 09/11/2021 at 17:36

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p-p-xfmr.png

Generic schematic for push-pull transformer stage

Portable Network Graphics (PNG) - 11.14 kB - 09/11/2021 at 17:36

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Screenshot_2021-09-09_21-26-31.png

Screen snip from TI SN6505A data sheet. This shows open loop control and non-overlapping timing. PWM duty is maximum.

Portable Network Graphics (PNG) - 38.18 kB - 09/10/2021 at 01:28

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