All pins compatible except:

    Skt.    RAM
31    PU    A15 wire to A15 on skt pin 29
29    A15    !WE flying wire to CPU.9, TPAL.8, U55.12, or U54.13
24    !OE    !OE wire to Skt. 22 (which is !RD)
22    !CE    !CE

ROM.!OE is !ROMSEL

ROM.!CS is labelled BR/!W on circuit rev. A, and /R/W on  circuit rev. B.
The circuit shows it is inverted CPU R/!W, so it is more of a shared !RD signal.
That makes sense, but intuitively I would have expected the !RD to go to ROM.!OE and !ROMSEL to go to ROM.!CS.

Maybe OE access time is faster than CS?

Now the SRAM needs activating at the bottom block, I need to activate it there.

/RAMSEL is actually /DRAMSEL, it goes to TPAL.3 to activate the DRAM signals.
So I removed the link between pins 1 and 2 of link area P1 to disable the DRAM there.
To disable it everywhere, it would need a pull-up resistor.
So instead, I shall enable it just before the ROM.
IC59 decodes memory into eight 1-megaword blocks.
Two 512K SRAM chips would appear twice in a block.
I shall relocate the DRAM to block 4 at 0x400000, 
so that it is safely driven high.

A23 22 21 20     
0   0  0  0    !SRAM
0   0  0  1
0   0  1  0
0   0  1  1
0   1  0  0    !DRAM
0   1  0  1    !ROM
0   1  1  0    !IOSEL
0   1  1  1    !EVPA

 Next issue will be to drive the CPU !DTACK when SRAM is accessed.

One could do this by pulling the !EXTDTACK signal low.

This is the open collector signal from external devices on the expansion slots.

I don't have any expansion cards, so until I do I can wire the !SRAM signal straight to !EXTDTACK.

The system should then be able to boot up using SRAM.

No video, so it has to use the serial port as a user interface.

The DRAM should still be accessible for testing.

UPDATE:

ROM.!OE is !ROMSEL only on the original board, for EPROM chips.

For reasons discussed in Flash ROM issue, this should not be done for Flash ROM chips and the forthnutter board wired correctly. So /OE is in the right place for RAM chips.