Many people learn electronics as a join-the-dots exercise in textbooks written by academics who teach but seldom make practical products. Power lines are drawn with the same pencil-thin lines as signals, connections have zero resistance, inductance or capacitance, and so on.

Your CAD system will check you have made all the right connections, but it won't tell you if your thin copper track is going to melt as soon as a power transistor gets switched on. Well, as of 2026, but one day AI will be able to do this.

I have seen professional products designed by people with no appreciation of real-world current flow. Like the battery charger my employers once paid a lot of cash to a subcontractor to design. Heavy currents, thin wires... it did not blow up but it got hopelessly confused trying to measure currents. But that's another story,

Back to the board we are looking at...

Power rails

The power enters on the left, next to the expansion slots. This makes sense because the expansion board could take a lot of current, but I have none so is is not an issue. Or cause of problems that the board is having.

A good way of telling which chips are using the most current is to feel which are warm or hot. 

My NMOS CPU was rated at 8 MHz, and the board timings demanded at 10 MHz (or faster) part. I fitted a 16 MHz CMOS CPU, and that runs stone cold.

The NMOS SCC ran warm even when idle, so I bought and fitted a CMOS version. 

The 6845 CRTC is also running warm, but that seems to be running without errors so it doesn't seem to be starved of power.

DRAM is notorious for needing power, and huge gulps of it every time a row address strobe refreshes the charge on a row of capacitors. They are tiny, but there are many on a row and they need topping up in a fraction of a microsecond. Hence the huge current pulse, and the need for a decoupling capacitor for every DRAM chip.

Some people say that you really need power and ground planes for serious RAM designs, but these extra layers push up the board price. So board designers have to take more care for two-layer boards. 

The Applix 1616 has the DRAM chips on the opposite side of the power inlet. So all those row-charging current gulps have to travel through the copper tracks across the board, dipping the rails of everything else on the board. 

The BBC micro got round this by having power input connections specifically for the DRAM chips. This might be something worth adding to the Applix board.

Let's take a look at the voltage drops. 

First I set my PSU to deliver 5.2 volts on the power input of the board, then measure the voltage across the power pins of various chips.

5.008  Input measured at J13.

4.812 at CPU, ROM chips (3.76% low.

4.816 at CRTC

4.817 at SCC

4.847 at furthest DRAM chip (the worst case) is 3% drop, which is acceptable.

4.982 at U49

4.986 at U5 and U51, the PAL chips

4.990 at U2, , the IC nearest J13.

With 5.2 volts at J12, furthest DRAM is 5.035 volts.

So it looks like the 5V power is okay across the board.

Termination

I went to a lecture about the BBC micro, and the speaker said that the BBC failed to run reliably until someone held their fingers on the board tracks. They didn't know why, but they added some resistors to the data bus to simulate the resistance of fingers, and the BBC worked.

Well I could have told them straight away why it didn't work. When you have wires over a board the size of a BBC micro, they stop being a join-the-dots textbook wire and start behaving like a transmission line with inductance, capacitance and reflection. Fingers or resistors act as terminating loads, absorbing energy that would otherwise be reflected to cause overshoots and undershoots.

The Applix is about the same area as a BBC micro. But it does not have any bus termination at all!

Right, that needs sorting out!

Fortunately I have a known-good termination circuit from the STEbus. I'll start by tying the data bus to 2.8 volts via 270 ohm resistors. 270 ohms is the load applied to the 74LS245 buffers in an STEbus system. 

I did not have any 270 ohm resistor packs, so I briefly tried tying the data bus to 5V with 220 ohms. No better, possibly worse. A 220 ohm load to 5V is 20.45 mA. The 68HC000 I am using can only sink 5.3 mA, and an NMOS 68000 can only sink 3.2 mA. Reducing the data bus pull-ups to 10k did not help, the system is back to 1 or 2 exceptions then stopping.

I wondered if the timing was very 'on the edge'. Changing to an 8 MHz CPU made this worse.

I have bought a 10 MHz rating chip to try out.