In simulation, the D-latch does not work when provided with the intended inputs. This is because we did not take into account the analog behavior of the 555 when designing our digital model.

For our next analysis, table 3 in the datasheet does not totally describe the behavior when the Control pin is being used.

Observing Figure 1 from the datasheet shows that there is a voltage divider chain of 3 resistors connected between V_DD and GND, with the Control pin connected to the node between the first and 2nd resistors. (This is one of the defining characteristics of the 555.)

The Threshold pin's comparator's inverting input is taking from the same node the Control pin is connected to. And the !Trigger pin's comparator's non-inverting input is taken from a node that is between 2 resistors; one end of which is Control and the other is Ground.

So when Control (C) is driven (not floating), the voltage that Threshold compares against is C, and !Trigger compares against C/2. Our new table is:

We need to choose carefully our input voltages so that we obtain the desired D-latch behavior. For the sake of simplicity, we will assign V_DD an imaginary voltage of 1 and GND an imaginary voltage of 0. When we get to our actual power supply, we can scale up accordingly.

We only have one state we need to worry about when the latch is disabled; this is the "Output stable" state from our table.

1. Th should always be below C, so let's make Th 0 and have C always be above 0
2. !Tr should always be above C/2, so let's make !Tr 1 and C always be below 1.

Now we need to think about the inputs when our latch is enabled and allowing the Data input to pass through to the output. This is rows 2 and 4 of our table (!Reset H, Output is either H or L).

1. Th is "don't care" when Output is H, and above C when Output is L. So let's make Th 1 and have C always below 1.
2. !Tr is the trickier one. It needs to be greater than C/2 when C is low, and less than C/2 when C is high.

So assuming our C goes from 0 to 1, !Tr needs to be somewhere between 0 and 0.5. Let's give ourselves plenty of margin and split the difference, and have !Tr at 0.25.

Of course, our C can't go to 0 or 1, per our previous constraints. Let's make it go from 0.2 to 0.8, again giving plenty of margin between the rails.

Now, you may have noticed that our Th and !Tr are not exactly complementary anymore, and we relied on them being opposites when we built a D flip-flop from our D latches. We may have to have 4 clocks in to our D flip-flop, differing by going through a voltage divider or not.

Then again, maybe we can figure out a way to keep our clocks complementary. Notice that when our latch is disabled, Th just needs to be below C. If we make C always above 0.25 then we can let Th be 0.25 and keep complementary clocks. Let's instead have C go between 1/3 and 2/3. And then when the latch is enabled, !Tr needs to be greater than 1/6 and less than 1/3. 1/4 is 3/12 which is exactly between 2/12 (1/6) and 4/12 (2/3) so we are good to have complementary clocks again.

So how do we achieve these voltage levels? With resistive voltage dividers. For our clocks, we can use a pull-up value of 3R and a resistor value of R from the input clock signal. For our C signal (which is our data input), we use equal values for each of pull-up, pull-down, and resistor on our data line.