We have solved the analog voltage levels, but a simulation of our D flip-flop still does not work as designed. What gives? This issue took a lot of time for me to figure out. Experienced logic designers likely saw the issue once I mentioned that the latch has 2 complementary clocks.

The problem is that our design relies on 2 different signals switching at exactly the same time. In the real world, almost nothing happens at exactly the same time.

This is especially the case when the clocks are coming from a previous counter stage, where one clock output comes from a flip-flop, and then goes through an inverter to the other clock output, experiencing one logic delay.

We need to be especially concerned when the latch goes from enabled to disabled. Any glitches here could cause the latch to flip to the wrong state, and stay there. Let's take a look at our table again:

Recall that when the latch is enabled (i.e. in pass-through) Th is 1 and !Tr is 0.25. C is either 1/3 or 2/3. Let's play out a thought experiment with our clock changes to see how it goes.

1. If C is high, i.e. 1/3 then !Tr > C/2 and O is L.
   1. If we first flip !Tr to 1, it's still > C/2. O is still L, so we are good to then flip Th to 0.25 to go stable.
   2. If instead we first flip Th to 0.25 then Th < C and !Tr was already > C/2 so we're now early in stable state and when !Tr next goes to 1, we're still stable.
   So the order of clocks change doesn't matter when C is low.
2. Now let's consider C high, i.e. 2/3. !Tr < C/2 and O is H.
   1. If we first flip !Tr to 1, now !Tr > C/2 and Th was already > C. O goes L. Uh-oh. We shouldn't flip !Tr first.
   2. Let's see if we can flip Th first instead. If we flip Th to 0.25 then it's < C. !Tr is still < C/2 so O is still H when we next flip !Tr to 1 to go stable. Phew.
   So we must flip Th first.

How do we make sure that Th always flips first? We take the Th input clock signal as early as we can in our chain of logic, and make sure that the !Tr is derived from the Th signal by going through an inverter, experiencing one logic delay. This will necessitate one extra 555 per counter.