PavelALU instructions make use of the main ALU to perform arithmetic and logic operations on data stored in 8 General Purpose Registers.
The results of these operations are stored in One of the GPR and in Status Register (flags indicating some aspects of operation results that can be then used as conditions for branching).
All ALU instructions are taking up a single word, and need one clock cycle to fetch and one to execute. ALU instruction cycles are staggered, the execution of the the ALU instruction is in parallel with the fetching of the next instruction. In case of several ALU instructions in a row, throughput is 1 instruction per clock cycle.
Other instructions can be investigated here: General layout of instruction types.
There are several types of ALU instructions:
1) arithmetic and logical operations between a 16-bit value in register and 8-bit constant hard coded into instruction word (immediate ops):
Instruction bits
Mnemonic: F E D C B A 9 8 7 6 5 4 3 2 1 0
ADDi rA 0xFF 1 0 0 0 1 a a a c c c c c c c c
SUBi rA 0xFF 1 0 0 1 1 a a a c c c c c c c c
XORi rA 0xFF 1 0 1 0 1 a a a c c c c c c c c
XNORi rA 0xFF 1 0 1 1 1 a a a c c c c c c c c
ORi rA 0xFF 1 1 0 0 1 a a a c c c c c c c c
ORNi rA 0xFF 1 1 0 1 1 a a a c c c c c c c c
ANDi rA 0xFF 1 1 1 0 1 a a a c c c c c c c c
ANDNi rA 0xFF 1 1 1 1 1 a a a c c c c c c c c
a - bits of register address(A) where 16-bit value comes from,
and result is written to
c - bits of hard coded 8-bit constant
A - number in range 0-7, this is register address
0xFF - constant in range 0-255
2) Arithmetic operations between two values from registers, with write to third register: Add, Subtract, Add with Carry and Subtract with Carry:
Instruction bits
Mnemonic: F E D C B A 9 8 7 6 5 4 3 2 1 0
ADD rY rA rB 1 0 0 0 0 y y y a a a 0 0 b b b
SUB rY rA rB 1 0 0 1 0 y y y a a a 0 0 b b b
ADDC rY rA rB 1 0 0 0 0 y y y a a a 0 1 b b b
SUBC rY rA rB 1 0 0 1 0 y y y a a a 0 1 b b b
a - bits of register address A of the first operand
b - bits of register address B of the second operand
y - bits of register address Y for result to be written to
A, B, Y - numbers in range 0-7, they are register addresses
3) Logic operations between two values from registers, with write to third register
Instruction bits
Mnemonic: F E D C B A 9 8 7 6 5 4 3 2 1 0
XOR rY rA rB 1 0 1 0 0 y y y a a a 0 0 b b b
XNOR rY rA rB 1 0 1 1 0 y y y a a a 0 0 b b b
OR rY rA rB 1 1 0 0 0 y y y a a a 0 0 b b b
ORN rY rA rB 1 1 0 1 0 y y y a a a 0 0 b b b
AND rY rA rB 1 1 1 0 0 y y y a a a 0 0 b b b
ANDN rY rA rB 1 1 1 1 0 y y y a a a 0 0 b b b
a - bits of register address A of the first operand
b - bits of register address B of the second operand
y - bits of register address Y for result to be written to
A, B, Y - numbers in range 0-7, they are register addresses
4) Two-operand operations without writing the result (operations CMN, TST and TEQ are taken from ARM ISA described on this page):
Zero flag is set when result is True, except for TST where Zero flag is cleared for True.
Instruction bits Mnemonic: F E D C B A 9 8 7 6 5 4 3 2 1 0 TEQ rA rB 1 0 1 0 0 x x x a a a 0 1 b b b Test equivalence (rA XOR rB) TCM rA rB 1 0 1 1 0 x x x a a a 0 1 b b b Test complement (rA XNOR rB) CMN rA rB 1 1 0 0 0 x x x a a a 0 1 b b b Compare Negative (rA + rB) CMP rA rB 1 1 0 1 0 x x x a a a 0 1 b b b Compare (rA - rB) TST rA rB 1 1 1 0 0 x x x a a a 0 1 b b b Test bits (rA AND rB) TIB rA rB 1 1 1 1 0 x x x a a a 0 1 b b b Test inverted bits (rA ANDN rB) a - bits of register address A of the first operand b - bits of register address B of the second operand x - "don't care" bits - have no effect on result A, B - numbers in range 0-7, they are register addresses
5) 1-bit shift operations:
Instruction bits Mnemonic: F E D C B A 9 8 7 6 5 4 3 2 1 0 SHL rB rA 1 0 1 0 0 d d d s s s 1 0 0 x x shift 1 bit left SHR rB rA 1 0 1 1 0 d d d s s s 1 0 0 x x shift 1 bit right ROLC rB rA 1 0 1 0 0 d d d s s s 1 1 0 x x rotate through carry 1 bit left RORC rB rA 1 0 1 1 0 d d d s s s 1 1 0 x x rotate through carry 1 bit right ASHL rB rA 1 0 1 0 0 d d d s s s 1 x 1 x x arithm shift left, same as regular shift ASHR rB rA 1 0 1 1 0 d d d s s s 1 x 1 x x arithmetic shift right, when msb is copied to the right s - bits of source register address A, where value is coming from d - bits of destination register address B, where result is written to x - "don't care" bits - have no effect on result A, B - numbers in range 0-7, they are register addresses
6) Multi-bit rotations -- the set number of most significant bits get moved to be least significant bits in word:
Instruction bits Mnemonic: F E D C B A 9 8 7 6 5 4 3 2 1 0 ROTi rY rA 0xF 1 1 0 1 0 d d d s s s 1 n n n n Rotate 0xF (0-16) bits left ROT rY rA rB 1 1 0 0 0 d d d s s s 1 x r r r Rotate (value in reg rB) bits left s - bits of source register address A, where value is coming from d - bits of destination register address Y, where result is written to n - bits of the rotation number 0xF r - bits of register address B where rotation number is coming from x - "don't care" bits - have no effect on result A, B, Y - numbers in range 0-7, they are register addresses When rotating by value from register rB, the 4 least significant bits of rotation value are used.
7) Byte sign extend - copy bit 7 into bits 8 through F:
Instruction bits Mnemonic: F E D C B A 9 8 7 6 5 4 3 2 1 0 BSE rB rA 1 0 0 x 0 d d d s s s 1 x x x x s - bits of source register address A, where value is coming from d - bits of destination register address B, where result is written to x - "don't care" bits - have no effect on result
8) Invert - change all 0s to 1s and all 1s to 0s:
Instruction bits Mnemonic: F E D C B A 9 8 7 6 5 4 3 2 1 0 INV rB rA 1 1 1 x 0 d d d s s s 1 x x x x s - bits of source register address A, where value is coming from d - bits of destination register address B, where result is written to x - "don't care" bits - have no effect on result
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