News from Renesas about availability:

https://community.renesas.com/gpak-gfet/f/greenpak-greenfet/29049/forgefpga-availability

Basically, parts shall be available late Q2 2023.

I just receeived notice from Mouser that the SLG7DVKFORGE development board I ordered in April has shipped. The shipment is by UPS Ground, so I'll probably get it on Monday. David says he received his already and that it included the SLG47910V-SKT socket adapter and some sample chips. I already have two of the socket adapter and some sample chips, but presumably the DVK will include the newer version of the socket adapter. (Not that the differences are important.)

I still have two of the SLG47910C-SKT socket adapters (with samples) backordered for the 20-pad WCLSP part, but that's of much less interest.

The data sheets for the SLG47910 chip, the development board, the socket adapter, and (presumably) the low-cost evaluation board are still only available on request from Renesas. I've got the 2.1 data sheet and versions of the socket adapter manual for two different revisions of the socket adapter, but I have not yet been able to get the manual for the development board or the evaluation board. I have just emailed Renesas a request for this documentation, and an updated datasheet if there is one newer than revision 2.1 dated 3-Feb-2022.

A new release of the development software became available a few days ago. I use Fedora Linux, which isn't directly supported, so previously I'd installed their Ubuntu version into a virtual machine. With this new release, I tried runing their Debian dpkg through "alien" to convert it to an RPM. A little bit of elbow grease was required to avoid trivial directory ownership conflicts, but I was pleasantly surprised that the resulting RPM works fine on Fedora 36.

Here is a link to the revision 2.3 of the part datasheet (13 June 2022).

https://community.renesas.com/cfs-file/__key/communityserver-discussions-components-files/293/SLG47910_5F00_ds_5F00_2v3.pdf

The schematic for the dev board would be interesting to have a look at the programming circuit. 

In the latest "go configure sw hub" development software, version 6.3.001, and in the latest ForgeFPGA application note, an-fg-011_4-bit_counter_with_emulation, there are illustrations of a "ForgeFPGA Evaluation Board". This appears to be a lower-cost board for ForgeFPGA development, although I can't find any announcement of the board, and distributors don't list it yet, so I don't know what the price will be. The board has a soldered down SLG47910V, two dual-PMOD connectors for GPIO 00 through 15, dual-row headers for all the pins, and a USB-C connector. There's a microcontroller that handles the USB and allows the dev software to download to the ForgeFPGA in "emulation" mode, which is what Renesas calls downloading to FPGA configuration RAM without programming the OTP.

I managed to get my hands on one of these boards (but no documentation yet), and have successfully downloaded and tested a version of the AN-FG-001 four-bit counter, which I extended to a twelve-bit counter. This is the first time I've actually gotten anything running on a ForgeFPGA, and it works fine. The application note runs the counter on the internal oscillator, which according to version 2.1 of the preliminary datasheet (dated 3-Feb-2022) has a range of 47.7 to 51.62 MHz.  My logic analyzer shows the low-order counter bit oscillating at about 22.7 MHz, so the internal oscillator must be around 45.4 MHz, a little lower than the datasheet spec. However, the datasheet specifies that for Vddio = 3.3V and Vddc = 1.1V +/-10%, and the evaluation board doesn't offer that specific configuration. The software has popups to select Vddio and Vddc, but while the datasheet specifies their ranges independently (Vddio = 1.71V to 3.63V, Vddc = 1.1V +/-10%), the software offers a limited selection of discrete choices, and the Vddc and Vddio choices are not independent. For example, the default seems to be Vddc = 1.2V and Vddio = 2.3V. Vddio = 3.3V is not offered, and I can't select Vddio = 3.0V without increasing Vddc to 1.5V, significantly out of spec.

I don't have the $250 development board, but I do have the SLV47910V-SKT socket adapter, which is intended for use with that, and comes with ten sample chips. The socket adapter is designed to be useful standalone, but does not function as a programmer or downloader, I have attempted to create my own RAM downloader in Python, using an Examera SPIDriver as the USB to serial interface. The Renesas software does not support that. I wrote the Python code based on the Renesas configuration guide. So far I do not have that working. I plan to use the logic analyzer to capture the SPI data when the Renesas software downloads to the evaluation board, and see whether I can determine what my Python program is doing wrong.

AN-FG-011 also describes using their development software as a logic analyzer to monitor the GPIO pins when using the chip in emulation mode. The application note doesn't explicitly state it, but I think that logic analyzer functionality requires the $250 development board rather than the evaluation board.

Mouser now shows two week factory lead time for the SLG47910V-SKT (socket adapter with 50 samples), with eight expected on July 26th (three weeks away). There's been no update on my order from April 26th, when the lead time was one week. I'm getting impatient.

At this point my uneducated guess would be, that there was a problem with the latest revision of silicon and a new fab run takes months, even with Renesas being in the lucky position to have in-house fabs. 

I received an update today on my orders - the FORGE development board still has no date; I had coupled a SLG47910V-SKT order with a SLG47910C-SKT order in order to get free duty-paid shipping (I'm in Canada). The 47910C variant still shows with no delivery date, but the email indicated that the 47910V unit was in stock, implying that the first shipment had already arrived (the date you see would be for any not-yet-preordered units). I will not revise my orders until the dev board is in stock (or the 47910V chip is generally available), so I won't be be getting mine this week.

But I would be curious to see if anybody else receives theirs this week.

And Mouser's price increased today by 66% for the SLG47910V-SKT .  Now it's $86.25CDN ($62.50US)

...And they also revised the part description to include only 10 samples rather than 50, as previously listed.

That's a pretty big change.

No separate listing of the parts either (without the devboard socket).

I got email from Mouser that they have my two SLG47910V-SKT in stock, and waiting for the rest of the backorder. It said to contact them if I want the stock items shipped, so I just did that, and it's supposed to ship this afternoon. I had selected UPS ground shipping, which usually takes two to three days, so I should have them on Tuesday or Wednesday. Since I won't yet have the main dev board, I need to hack up something to do the SPI loading of the bitstream.

Since the product description changed from 50 samples to 10, it will be interesting to see what I get. It should be 50 since that was the description when the order was placed, but I'm not betting on it.

I hope parts become available for normal purchase soon,but I'm not holding my breath on that either. I'd also like to see information on the 2K part. I'm hoping for more I/O pins.

The two SLG47910V-SKT socket adapters with samples arrived today (2022-08-02). Here are a few photos taken with my cell phone; I'll try to take better photos of the socket adapter board later with a good camera.

https://www.flickr.com/photos/_brouhaha_/albums/72177720301009166

They did in fact come with only ten samples each, per the updated description, v.s 50 samples in the description at the time I ordered. I have reached out to Mouser about the discrepancy. I think Renesas is contractually obligated to remedy this shortfall.

The worse problem is that the documentation (including schematic) for the SLG47910V-SKT was not provided, nor is it on the Renesas web site. The socket adapter should be usable in a standalone configuration, without the dev board (which is still backordered), but it will be difficult to use it without at least the schematic. I have emailed Renesas, but it took them over a month to respond to my request for a datasheet, so I'm not holding my breath. I also asked Mouser whether they could get it; it seems likely that Renesas might take requests from their distributors more seriously than requests from the general public.

I really don't understand what benefit Renesas believes they realize from not making the datasheet, dev board manual, and socket adapter manual publicly available on their web site.

Renesas responded to my email request for the SLG47910V-SKT manual in less than 48 hours, and emailed me the PDF. It's for a newer version of the board than what I actually received. There are a lot of differences, but enough similarities that the doc is still useful.

The socket adapter board I received has:

* Dialog branding

* DIP switches to connect/disconnect GPIO pins to the edge connector (for the eval board)

* Seven uncommitted user LEDs, connected to a single row 100 mil pitch header, which could be ju,pered to GPIO pins

* Silk screen on bottom of board lists one of the power inputs as "+5V".  It's better to use 3.3V or VccIO; See below.

The socket adapter board described in the manual has:

* Remesas branding

* no DIP switches

* no uncommitted user LEDs (though the front page lists them as features)

* Silk screen on top of board lists one of the power inputs as "+5V". Schematic says 3.3V. it powers the 74HC4066 analog switches and an I2C ID PROM, which shouldn't be damaged by 5V,  but in my opinion it's better to use 3.3V (or VccIO), and in fact it's connected to 3.3V if you use the dev board.

Since I don't have the main development board, I need to provide Vdd(core) of 1.1V and Vdd(io) of 3.3V myself, which is no big deal. The socket adapter has an SPI flash, and jumpers to connect or disconnect it from the FPGA. With it disconnected, I should be able to use SPI from my computer to directly load the config into RAM of the FPGA. There appears to be enough info in the configuration guide, which is on the Resensas web site, to accomplish that.

In that SPI bitstream, right after the sync word, there are "288-bits data used to configure other SOC registers", with no further elaboration as to exactly what these registers are, and AFAICT the bitstream generation process does not produce them. Later they do say "Default all zeros", so I'll try that. More explicit detail in the documentation would be nice.

The config guide should have explained exactly how to map the bitstream into the SPI flash, but it doesn't. It's likely similar to slave mode loading, but they don't say whether the SPI flash needs to contain the all zeroes preamble, sync word, "other SoC registers", or postamble.

Similarly, although they give info on programming the internal OTP, they don't specify how to map the bitstream there either.

If one wanted to know the details of putting the bitstream in SPI flash or internal OTP, maybe one could ask Renesas, but if they had that info in any presentable form, they probably would have included it in the config guide. It may be easiest just to wait for the eval board, and use a logic analyzer to monitor how they do it. For my own purposes, I'm fine with using SPI slave mode for now.

I expect to load some simple test bitstreams in SPI slave mode tomorrow night or over the weekend.

Oh, this is exciting. Finally some good news. Nice pictures of the adapter board, which looks quite usable on its own. And you are making some progress with access and programming already. I have to bump this up again on my long to-do list. 

I received a shipment confirmation from Mouser on a GreenPAK development board from Mouser, which had also been out of stock (note: this is not the FPGA one).

This was a surprise with no advance warning, so I checked stock levels of the FPGA-related parts. Still no delivery date update for the Dev Board (SLG7DVKFORGE), but the FPGA chip (SLG47910V-SKT) now shows as being expected June 27.  Cross your fingers.

This is exciting. Fingers crossed. I am also monitoring the Mouser website and should get an email notification when anything is in stock.

Well, to add further confusion to all of this, all of the Dialog Semiconductor information has been ported to the Renesas.com website.  Looking at the documents, some have been rebranded (which is a reason for an updated publication date), but I haven't seen any new content or information in the 'updated' documents; only rebranding.

- Some links don't work.

- The Go Configure Software Hub v6.30 still points to links at the dialog site.

-> This may temporarily slow down requests for information.

Landing page for the FPGA stuff is here:

https://www.renesas.com/us/en/products/programmable-mixed-signal-asic-ip-products/forgefpga-low-density-fpgas#document

Separately, I have also received similar 'expediting in progress' updates from Mouser (more recently than listed below). It appears that actual release date is still not clear to the supply chain.

I threw together an Eagle 7 library with the SLG47910C and SLG47910V. This is totally untested and likely has mistakes,, so of course there is NO WARRANTY.

There's conflicting information on whether the QFN has a thermal pad. I haven't seen the actual chip yet, but the package outline doesn't show a thermal pad so I didn't put one in my Eagle footprint.

http://www.brouhaha.com/~eric/fpga/slg47910.lbr

Nice. Thank you very much for contributing to the good cause.

I have not used Eagle in almost a decade, but might try the KiCAD import (if it does libraries) with this one.

How is the status of your dev board order?

In the meantime, I contacted Renesas and they sent me the datasheet, no problem. Lots of good stuff to read.

Maybe they don't like me because my email address is @gmail.com.

My order status with Mouser shows "will advise" for the dev kit and both models of socket adapter boards.

What's the date and/or revision of the datasheet you received?

I'd really like to see the schematic of the socket adapter board. Maybe it will be included with the socket adapter, or with the dev kit. Maybe you could request the docs on the dev kit and socket adapters from Renesas.

I just got email from Mouser with an order status update. The estimated ship dates for the dev board and the socket adapters is still "Will Advise", and the socket adapters still say "ordered from factory", but the dev kit has changed from "ordered from factory" to "expediting in progress". I'm not sure if that really means anything.

Renesas is still not replying to any of my email, even after I sent a new request a week ago from a different email address that isn't at gmail.com.

Renesas finaly today (June 17th) replied to my email request of May 5th, and sent me version 2.1 of the SLG47910 datasheet, dated February 3rd. The eval board and socket adapter/sample kits, quoted 1 week lead time when I ordered from Mouser on April 26th, are still backordered.

I got the same version datashseet, and it was already branded Renesas. Let's see what happens on June 27th.

I just ordered the Dialog development board and socket adatper/sample kits from Mouser. They're quoting 1 week lead time, but we'll see.

At least they're not quoting 52+ weeks like nearly all other FPGAs, CPLDs, and micrcontrollers. Maybe they'll actually arrive within my remaining lifetime.

I also requested the preliminary datasheet from Renesas, but haven't heard back yet. I understand that it's preliminary, but they should just put it on their web site. It's been common practice for more than 50 years for IC vendors to publish preliminary data sheets, and everyone knows what "preliminary" means.

According to the configuration guide, which IS available for download, the config cells in the part are RAM, and they can either be loaded over SPI, either from a SPI flash chip or from a microcontroller) _OR_ from the internal OTP cells at power-up. Clearly the latter is what they expect people to do in production, but it sounds like development isn't going to require throwing away a lot of OTP devices, except perhaps if your design can't spare the SPI pins. For my purposes, I might use the SPI loading even for production.

The socket adapter boards can plug into the development kit board, but it looks like they are also useful in a standalone capacity. They bring out most of the GPIO pins to PMOD headers, and there's a header to supply power (if you don't have it plugged into the main development kit board).

Interesting details. I would be interested to know how the order goes. At least for the socket adapter, they are claiming 2 pcs expected 2022-05-04. Fingers crossed for your order.

Available datasheets, even preliminary (as you said) would be nice.

If you contact Dialog and let them know your goals, they will send you a (preliminary) datasheet for the products.  Lots of electrical values etc. are not yet finalized yet though (they seem to be finalizing these), which is likely why this is not yet public.

I wasn't able to obtain samples through Dialog (yet), and all of the links inside of GoConfigure software go to "you need access" areas on the Dialog website (even though I have an account which should provide me access to these things).

...However, I did see these SKUs appear on Mouser:

SLG7DVKFORGE - Dialog Semiconductor ForgeFPGA Advanced Development Board

SLG47910V-SKT - Dialog Semiconductor Dialog Semiconductor SLG4SA24-30x30 socket adapter, 50 SLG47910V samples. For use with - SLG4DVKADV

I believe that last part about "for use with" is wrong, and should instead refer to the development board I listed above (As the GoConfigure Workshop states).

The datasheet clearly states that the FPGA can receive its configuration from (a) OTP NVM, (b) external SPI (makes use of 4 of the GPIOs), or (c) from a microcontroller.

Due to the cost of the FPGAs (they stated less than a dollar), they seem to be assuming that the additional cost of external configuration memory would be prohibitive, which appears to be why they keep referring to OTP memory.

I am assuming that the "Advanced Development Board", at that cost, will provide access to all of these functions and more (i.e. probably some form of in-circuit analysis), as well performing one-time-programming if desired (but on a unit-by-unit basis).  But there doesn't appear to be any public information available on any of this yet.

Thanks David. Those are a lot good comments and encouraging for me to continue with this project. In-circuit analysis debugging would be a nice feature, which is the most powerful debug tool with all the other vendors.

They were scheduled to arrive at (and be shipped from) Mouser today, but seem to have missed that schedule. I'll keep watching.

I've tried contacting them two weeks ago, and again a week ago, and haven't heard anything yet. I'd really like to get the preliminary data, because I want to start my PCB layout. I've got the eval board and socket adapters on order. Mouser still quotes one week factory lead time, but it's been two weeks, and shortly after I placed the order Mouser changed the status to "will advise".

I didn't have any trouble registering and downloading the development software. I'd hoped maybe that would include the preliminary datasheet, but it doesn't.

I tried contacting them a week ago from an address that is NOT at gmail, and all I get is the same resounding silence. Getting rather frustrated.

Quoting your description:

"The user creates their circuit design by programming the One-Time Programmable (OTP) Non-Volatile Memory (NVM)"

OTP? that's useless

I know. With the lack of datasheet, I'm guessing the SPI flash will be the volatile memory for development. A cost optimized product will use the OTP. Without the need of external memory.

Also this is probably the reason for their low power claim. 

We'll see.

Well it says the dense logic section can be configured either via NVM (the OPT), or SPI. It's possible there might be some things (like the PLLs) that need the NVM to be set up - but hopefully not.

Hmm, maybe that's why Mouser SLG47910V-SKT says '50 SLG47910V samples' in its description. Maybe that's the way to go when prototyping: you made a small typo in your HDL? Get a new chip! :-)

Interesting catch with the 50 parts. This might be a source to get samples, maybe not cheap depending on the price of the dev kit.

The '50 samples' seems to be aimed at giving enough to make test boards (i.e. prototypes of final hardware, rather than development boards), after using the dev kit for the initial development. Test cycles on development would need many more than that. If you needed a new chip for each test iteration, you may need hundreds !  They seem to be aiming for sales of thousands per design, so 50 units can be treated as a mere consumable. They use this same model for their GreenPAK chips too.

By the way, the SPI load is triggered by holding one of the GPIOs high (the one used for chip select if using SPI) for a period at startup time... though I'm not clear on whether than needs to be brought low on a timer, or whether a pull-up would suffice... as the device itself would be driving this line low in order to load configuration from SPI.

The press information focuses on OTP because that's what they expect customers to use for production. However, according to the configuration guide (available on the Renesas site), the FPGA is RAM based, and the RAM config can be loaded from SPI, either with the FPGA as a master reading from an SPI flash chip, or with the FPGA as an SPI slave being configured from a microcontroller. You give up four GPIO pins (GPIO 3 through GPIO6, out of 19 total GPIO pins) for the SPI interface,