Microcode Design in Progress for A1 with a Newly Modified Bus Architecture

The targeted decoding ROM is going to have 8-bit output. Under such restriction, the number of microcodes has to be not grater than 2^8 = 256 = 16 x 16.

Operation / Data Flow	Coding Space	Comment
B < B1 < Bus-C < Reg B > B0 > Bus-B > Reg	2 x 16	Totally 16 registers in reg-file
A1 < Bus-C < Reg A0 < Bus-C < Reg	2 x 16
B < ALU < Bus-A < A1A0	2 x 16	74LS181 has 5 lines selecting 2 modes by 16 functions
PC1 < Bus-C < Reg1 PC0 < Bus-C < Reg0	1 x 16	PC1 may only be loaded with odd numbered registers. 1 x 8 PC0 may only be loaded with even numbered registers. 1 x 8
PC1 > Bus-A > ALU > B >> Reg1 PC0 > Bus-A > ALU > B >> Reg0	1 x 16
MEM < Bus-C < Reg MEM > Bus-B > Reg	2 x 16
C1C0 < Bus-C < Reg	1 x 16
D1D0 > Bus-B > Reg	1 x 16
SL(B)1 SL(B)0 SR(B)1 SR(B)0	4	Shift Left (B) one bit and fill 1 Shift Left (B) one bit and fill 0 Shift Right (B) one bit and fill 1 Shift Right (B) one bit and fill 0
0(ALU) > B1 > Bus-C > MEM 1(ALU) > B1 > Bus-C > MEM 0(ALU) > B1 > Bus-C > C1C0 1(ALU) > B1 > Bus-C > C1C0	4	All bits with 0 All bits with 1 Generated by ALU 74LS181
C1 > D1 C0 > D0 C1 > D0 C0 > D1	4
IO < C1 IO < C0 IO > D1 IO > D0	4
IMM > D0 IMM > D1	2
IMM > IO	1
0(ALU) > B > Bus-B > CycleCounter	1	Reset CycleCounter to 0
StatusFlag < Bus-B < B0 < B	1
IR < Bus-B < MEM	1	Fetch instruction from memory
A++	1	32-bit {A1, A0} increase by 1
PC++	1	32-bit {PC1, PC0} increase by 1
number of microcodes in total	216	= 6 x 2 x 16 + 4 x 4 + 2 + 6

An extra "SILENT" operation, to silent all buses and control lines, with the ClockCounter still working increasing, might also need be coded.

The bus architure has been modified again to make coding in 16x16 feasible. Also smaller number of ICs is preferred.

A1 bus architecture v3 — Fig. Bus Architecture v3 for A1

Design Progress in Bus Architecture for A1

Revision of Bus Architecture for A1

Discussions

Become a Hackaday.io Member