I2C Master SDA & Slave SDA Monitor Out

I2C Master & Slave SDA lines connect together, so monitoring them individually with a scope or data analyser has been impossible, UNTIL NOW

Description

I2C master and slave SDA lines connect together, so monitoring them individually by oscilloscope or data analyser is impossible, UNTIL NOW, that is.
Designed for standard I2C speed of 100Khz, this project enables the separate monitoring of Master SDA and Slave SDA lines, while still enabling communication in either direction between the two. I searched Google high and low for someone who had already done this , but could find no-one.
There are plenty of I2C isolation designs out there, but none with the added separate Master and Slave signal output facility.

Details

4 Channel Data Analyser screen dump.

From top to bottom:

Composite SDA

Master SDA

Slave SDA.

SCL.

Logic Analyser

Rough and ready test PCB

This project is ideal for learning about the I2C protocol if you're new to it, because you can clearly see each and every transition and who's doing the transitioning.

Normally it is only possible to monitor the composite SDA line which carries both master and slave data, so it's hard to know who is sending the ACK pulses or who is holding the line low or answer the question: 'What are those narrow pulses all about' ? etc. etc.

By using a cheap multi channel data analyser ex AliExpress, plus this project, you can view all 4 channels ie. Composite Master/Slave SDA line, Separate Master line, Separate Slave line and SCL line on your PC with the free Saleae Logic 2 software. Download from www.saleae.com

A quick search of Aliexpress "USB Logic Analyzer 24MHz" will bring up plenty of units under US$10 incl shipping.

This project is a bit 'rough and ready' The schematic is hand drawn and there is no PCB artwork or .pcb files supplied. This is more than made up for by the detailed info supplied in this text.

It is designed so you can knock a board out with spare parts you may have lying around.

Circuit Diagram:

Desciption of Circuit :

I won't describe the isolation circuitry in full as it's a standard arrangement, better described by the likes of TI etc.

The two signals on lines labelled I/O Master SDA and I/O Slave SDA are separated with a standard dual opto coupler arrangement. I used the 6N137 ICs here due to their much faster switching times than their 6N138 or 139 cousins. 138 and 139 versions require 1K5 base bias resistors at 100Khz, between pin 7 and ground also. Pin 7 of the 6N137 has a different purpose and is an output enable pin. Pulled high internally, you can leave it open circuit. You can use any fast optos here though if you want to.

In addition to the standard I2C isolation arrangement circuitry sourced from TI's app notes, I've added two comparator gates which enable the Master signal and Slave signal to be filtered and output separately.

These comparators will only switch low when their associated 6N137's LED is active. ie. when 6N137's pin 6 is at GND level which is below the 1.21 volt comparator threshold.

The 1.21 volt comparator threshold, filters out the 1.38 volt LED Vf signal which is produced when the other non associated 6N137's LED is activated.

1.21 Volt comparator threshold was chosen due to the fact I had some 5K6 and 1K8 resistors available.

Any Vref between 1.38 LED Vf and pin 6 of 6N137 GND voltage will suffice.

___________________________________________________________

The comparators' pins 3 & 5 get to see 3.3v, 1.38v or GND levels depending on who's doing the switching.

A low going signal input to I/O Slave SDA will never reach pin 7 of Master comparator because its pin 5 input will see 1.38 LED voltage which is still above the 1.21 V threshold. The same applies to the duplicate I/O Master SDA circuit.

The Composite SDA signal line to the data analyser can be taken from either I/O Master SDA or I/O Slave SDA. They both see the same signal after all, separated only by the circuit's propogation delay.

The SCL lines wire directly between Master and Slave devices because the master alone (under most circumstances) has control of this line. The I2C spec does allow for the Slave to take control of this line under special circumstances, but I've never come across it. You could, however, have a duplicate circuit arrangement for SCL lines if you so choose. It's up to you.

NB: 6N137 optos and LMV393 comparators are powered with 5 volts for faster switching times than would be had from 3.3 volt supply. All 4 outputs are open collector devices...

Discussions

PinheadBE wrote 05/02/2022 at 22:29

What is the value of the Zener's ?

Are you sure? yes | no

Jeff Cooper wrote 05/02/2022 at 22:56

They are Schottky diodes. They are a metal-semiconductor junction instead of a semiconductor-to-semiconductor PN junction. One might consider them PN diodes with a Vfwd in the 0.3V range as opposed to 0.6 - 0.7 for small-signal PN applications.

They isolate the case where the instrumented SDA is passively high while the driving SDA is actively low.

Are you sure? yes | no

PinheadBE wrote 05/04/2022 at 03:42

I must have been very tired, because I thought I had s'en zoner diodes instead of Schottky. Anyway, thanks for the answer

Are you sure? yes | no

Jim wrote 05/03/2022 at 20:02

Each one is a Schottky diode, whose purpose is to enable the 6N137 pin 6 to pull I/O Master SDA or I/O Slave SDA to low level. This action also has the added function of pulling low the 6N137's LED anode, thus disabling it.

Are you sure? yes | no

indigoredster wrote 05/02/2022 at 19:12

Another way is to add a series res to each suspected device's SDA or SCL and use comparators to do a current sense across the series R. This shows which device is 'pulling'. OR if added in the middle of a path you can sense which side has the 'pulling' device, and narrow it down from there.

Are you sure? yes | no

Jim wrote 05/02/2022 at 20:12

Thanks for the info. That would at least do away with the need for the 6N137s and transistors etc. If I get some time, I'll have a look at the single $2 microcontroller idea. Even less parts required. Cheers

Are you sure? yes | no

crun wrote 05/03/2022 at 20:53

A couple of diodes is better than a resistor. See this:

https://www.i2cchip.com/pdfs/I2C_Clock_Stretch_Probe.pdf

If you have the kind of oscilloscope that can do maths/logic derived channels, it's easy to get it to generate a direction channel like Jim is doing in hardware,

If you use N pairs of schottky diodes (one pair to each device) as the bus hub, with the pullup at the centre star point, you can see exactly which devices are driving at any time on a complex bus.

Are you sure? yes | no

indigoredster wrote 05/03/2022 at 22:13

Excellent idea! then you can see it on the scope too. I've done differential across the R the way you mention. Sometimes it's easy just to lift a leg and insert an 0402, or a small trace cut and bridge it with the 0402.

Are you sure? yes | no

Jim wrote 05/05/2022 at 22:36

I knew there were always better and easier ways of doing things. Many thanks for your input.

Are you sure? yes | no

crun wrote 05/06/2022 at 22:03

@Jim

If you really get the urge to make a more sophisticated device to help with scope debugging etc, consider a silego part like: SLG46826

It has 4 comparators and logic, that can be reconfigured, and you can move pins about.

So you can make a device with specific outputs like an SDA contention output or a separate master and slave clock stretch outputs, or a data direction output, or a multimaster collision detector. Start / stop /busy outputs, leds with monostable pulse stretching etc. We had a couple of hardware devices doing this years ago, but the Silego approach is much more versatile and simpler hardware. Never released it for sale as not enough people will actually buy - mostly people will muddle by using a scope/logic probes.

If you are making multimaster systems, or systems using microprocessor based slaves, having hardware triggering on stretch and contention will let you find incipient and intermittent problems that are really hard to find just looking at the protocol and logic levels, and often remain hidden until a slight timing change

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Jim wrote 05/07/2022 at 21:40

SLG46826 looks very interesting. Thanks for pointing it out. Cheers.

Are you sure? yes | no

Jim wrote 04/28/2022 at 23:53

You're welcome. Cheers

Are you sure? yes | no

Ken Yap wrote 04/28/2022 at 23:51

Excellent idea. Will remember this option if I ever have to debug I2C comms.

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I2C Master SDA & Slave SDA Monitor Out

Description

Details

4 Channel Data Analyser screen dump.

Logic Analyser

Rough and ready test PCB

Circuit Diagram:

Desciption of Circuit :

Discussions

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Description

Details

4 Channel Data Analyser screen dump.

Logic Analyser

Rough and ready test PCB

Circuit Diagram:

Desciption of Circuit :

Enjoy this project?

Discussions

Become a Hackaday.io Member

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