Here are additional details you need to understand including the Control Pulse Matrix and the instructions.

The control pulses are the heart of the system. Each instruction has a sequence of control lines that are activated to cause data to flow through the system. Some of the control pulses have a control number in the control number column. These numbers came from the R-700 documentation. Through testing it was discovered there are a few minor errors in the matrix. I found another version that had the correct control pulses. These errors were in the multiply and divide instructions.

The following table is a combination of design and implementation. It lists each control pulse, where it originates and terminates on the hardware diagrams and what function is performed. The hardware diagram names are sub-system followed by module followed by sub-module. The Active State column can have a value of Low or High meaning the control pulse is active low or high, or values of Pulse meaning it is a pulse such as a clock pulse or a value of Bit meaning the value represents a bit value. Most of the control pulses are active low because many of the TTL chip inputs that are controlled are active low. That and many more of the TTL chips are active low logic. The few control pulses that are active high were chosen to be because that resulted in fewer chips required.  Just an FYI, this table formats better on my GitHub wiki page.

Control Line	Origin	Destination	Purpose	Cntl #	Active State
A2X	CTL-CPM-A	PROC-CRG-AREG, PROC-ALU	Copy A1-16 into X1-16 by private line (i.e. not through WL).	1	Low
B15X	CTL-CPM-A	PROC-ALU	Set bit 15 of X to 1	2	Low
BR1	CTL-SEQ	CTL-CPM-A	BR1 state	n/a	Low
BR2	CTL-SEQ	CTL-CPM-A	BR2 state	n/a	Low
CI	CTL-CPM-A	PROC-ALU	Set carry in bit into CI register. Adds 1 to adder value.	3	Low
CLXC	CTL-CPM-A	PROC-ALU	Clear X register if BR1=0. Used in Divide.	4	Low
CLISQ	CTL-CPM-C	CTL-SEQ	Clear the SNI bit	n/a	Low
CLK1	CTL-CLK	All	1 MHz Clock	n/a	Pulse
CLK2	CTL-CLK	All	1 MHz Clock	n/a	Pulse
CLK3	CTL-CLK	All	1 MHz Clock	n/a	Pulse
CLK4	CTL-CLK	All	1 MHz Clock	n/a	Pulse
CLRP	CTL-CPM-C	MEM-INT	Clear RpCell register	n/a	Low
DCDSUB	CTL-CPM-C	CTL-SEQ	Decode Sub-sequence	n/a	Low
DISP	CTL-CPM-B	DSKY-DSP	Write to Channel 10	n/a	Low
DVST	CTL-CPM-A	CTL-SEQ	Cause Divide staging by complimenting the next higher bit position. Sequence: 0, 1, 3, 7, 6, 4.	5	Low
DOTP1	CTL-SEQ	CTL-CPM-C	Do TP1 commands	n/a	Low
DOTP4	CTL-SEQ	CTL-CPM-C	Do TP4 commands	n/a	Low
DOTP6	CTL-SEQ	CTL-CPM-C	Do TP6 commands	n/a	Low
DOTP7	CTL-SEQ	CTL-CPM-C	Do TP7 commands	n/a	Low
DOTP10	CTL-SEQ	CTL-CPM-C	Do TP10 commands	n/a	Low
DOTP12	CTL-SEQ	CTL-CPM-C	Do TP12 commands	n/a	Low
EQU3	MEM-MBF	CTL-CPM-B	Instruction address = 3	n/a	Low
EQU4	MEM-MBF	CTL-CPM-B	Instruction address = 4	n/a	Low
EQU6	MEM-MBF	CTL-CPM-B	Instruction address = 6	n/a	Low
EQU17	MEM-ADR	CTL-SEQ	Inst. address = 17	n/a	Low
EXAMNXT	MEM-ADR_S	MEM-ADR-MDE	Examine next key pressed	n/a	Low
EXT	CTL-CPM-A, CTL-CPM-B	CTL-SEQ-SEQB	Set the extend bit.	6	Low
EXTEND	CTL-SEQ-SEQB	CTL-CPM-C, CTL-CPM-A, CTL-SEQ	>td >n/a	Bit
F10X	CTL-SCL	MEM-CTR-CTL	100 Hz timeout	n/a	Low
F13X	CTL-SCL	CTL-TPG	12.5 Hz timeout	n/a	Low
F17X	CTL-SCL	CTL-TPG	0.78125 Hz timeout	n/a	Low
FCLK	CTL-MON	MEM-ADR-MDE	Clock Mode	n/a	Low
GENRST	CTL-MON	All	General Reset	n/a	Low
G1	MEM-MBF	PROC-CRG-AREG	G reg bit 1 value	n/a	Bit
G16	MEM-MBF	PROC-CRG-AREG	G reg bit 16 value	n/a	Bit
G2LS	CTL-CPM-A	PROC-CRG-LREG, MEM-MBF-GMB	Copy G16,15-4,1 into L16,12-1 and X15	7	Low
GETBP	CTL-TPG	MEM-ADR-ATS, MEM-ADR-CTL	Get Breakpoint Address	n/a	Low
GMZ	MEM-MBF-GMB	CTL-SEQ-SEQA	G reg. is all zeros	n/a	Low
GP	MEM-EFM	MEM-PAR	Generate Parity	n/a	Low
GTR7	MEM-ADR-CTL	CTL-CPM-B	Address is > 07	n/a	Low
GTR1777	MEM-ADR-CTL	CTL-CPM-B, MEM-EFM	Address is > 01777	n/a	Low
INDC	CTL-CPM-B	DSKY-DSP	Write to channel 11	n/a	Low
INHINT	CTL-CPM-B	MEM-INT	Execute INHINT command	n/a	Low
INTR	CTL-CPM-C	CTL-SEQ	Perform Interrupt (RUPT)	n/a	Low
IRQ	MEM-INT	CTL-CPM-C	Interrupt requested	n/a	Low
ISBP	MEM-ADR-CTL	CTL-TPG	>td >n/a	Low
ISRUPT	MEM-INT	CTL-TPG	Is an interrupt pending?	n/a	Low
KB_STR	DSKY-KBD	MEM-INT	Key Strobe, data is latched	n/a	Low
KBD1	CTL-CPM-B	DSKY-KBD	Read Channel 15	n/a	Low
KRPT	CTL-CPM-A	MEM-INT	Reset the current RUPT priority (cell).	8	Low
L1	PROC-CRG-LREG	CTL-CPM-B	L register bit 1 value	n/a	Bit
L2	PROC-CRG-LREG	CTL-CPM-B	L register bit 2 value	n/a	Bit
L15	PROC-CRG-LREG	PROC-ALU	L register bit 15 value	n/a	Bit
L16	CTL-CPM-A	PROC-CRG-LREG	Set bit 16 of L to one.	9	Low
L2GD	CTL-CPM-A	MEM-MBF, PROC-CRG-LREG	Copy L1-14,16 directly (not through WL) into G2-15,16. Also set G1 bit if MCRO pulse is set.	10	Low
MANDATA	MEM-ADR-MDE	MEM-EFM, MEM-MBF-GMB	0 = AGC (normal ops), 1 = Manual Data	n/a	Low
MCRO	CTL-CPM-B	MEM-MBF-MBL	Part of the ZIP command.	n/a	Low
MONEX	CTL-CPM-A	PROC-ALU	Set bits 2-16 of X to ones, clear bit 1.	11	Low
MOUT	Only used by DINC, not implemented.	N/A	Causes generation of one minus drive pulse.	n/a	Low
NEACOF	CTL-CPM-A	PROC-ALU	Permit end around carry after end of MP3.	12	Low
NEACON	CTL-CPM-A	PROC-ALU	Inhibit end around carry until NEACOF.	13	Low
NISQ	CTL-CPM-A, CTL-CPM-C	CTL-SEQ	Set SNI bit. Next instruction to be loaded into SQ register. Permits increments and interrupts.	14	Low
PARALM	MEM-PAR	DSKY-DSP-IND	Parity Alarm	n/a	High
PIFL	CTL-CPM-A	PROC-ALU	Prevents writing into bit 1 of Y reg on a WYD pulse if bit 15 of L reg contains a 1. Used for DV instruction.	15	Low
PINC	CTL-CPM-C	CTL-SEQ	Execute PINC command	n/a	Low
PONEX	CTL-CPM-A	PROC-ALU	Clear X register and set bit 1 of X to 1.	16	Low
PSTGZ	CTL-SEQ-SEQA	CTL-CPM-C	PreStage is zero.	n/a	Low
PTWOX	CTL-CPM-A	PROC-ALU	Clear X register and set bit 2 of X to 1.	17	Low
R15	CTL-CPM-A	PROC-ALU	Octal 015 to WL's	18	Low
R1C	CTL-CPM-A	PROC-ALU	1’s compliment of octal 1 to write bus (WL's)	19	Low
R6	CTL-CPM-A	PROC-ALU	Octal 6 to WL's	20	Low
RA	CTL-CPM-A	PROC-CRG-AREG	Read A1-16 to WL1-16.	21	Low
RAD	CTL-CPM-A	CTL-CPM-B	Read address of next instruction. Appears at TP8 and normally interpreted as RG. If next instruction is INHINT, RELINT or EXTEND, it is interpreted as RZ & ST2 instead.	22	Low
RB	CTL-CPM-A, CTL-CPM-C	PROC-ALU	Read B1-16 to WL1-16	23	Low
RBBK	CTL-CPM-A	MEM-ADR-BNK	Read BB register onto WL's. FB16 to WL16,15 & FB11-14 to WL11=14 & EB9-11 to WL1-3.	27	Low
RB1	CTL-CPM-A	PROC-ALU	Octal 1 onto WL's	24	Low
RB1F	CTL-CPM-A	PROC-ALU	Octal 1 onto WL's if BR1=1.	25	Low
RB2	CTL-CPM-A	PROC-ALU	Octal 2 onto WL's	26	Low
RC	CTL-CPM-A	PROC-ALU	Read C register (B')	28	Low
RCH	CTL-CPM-A	CTL-CPM-B, PROC-CRG-RCHN, MEM-ADR-ATS	Read contents of channel address in S. Channel bits 1-14 to WL1-14 & bit 16 to WL15,16. Channels 1 & 2 same as RL and RQ	29	Low
REB	CTL-CPM-B	MEM-ADR-BNK	Read erasable bank reg	n/a	Low
RELINT	CTL-CPM-B	MEM-INT	Execute RELINT command.	n/a	Low
RFB	CTL-CPM-B	MEM-ADR-BNK	Read fixed bank reg	n/a	Low
RG	CTL-CPM-A, CTL-CPM-B	MEM-MBF	Read G1-16 onto WL1-16.	30	Low
RL	CTL-CPM-A	PROC-CRG-LREG	Read L1-14 to WL1-14 and L16 to WL15,16	31	Low
RLC	CTL-CPM-B	PROC-CRG-LREG	Read channel bus into L register	n/a	Low
RL10BB	CTL-CPM-A	PROC-ALU	Read B1-10 to WL1-10. Replaces c(S) by a 10 bit address.	32	Low
RPRO	CTL-CPM-A	DSKY-KBD	Read the PRO key from DSKY.	n/a	High
RPT	CTL-CPM-C	MEM-INT	Latch Interrupt Vector	n/a	Low
RQ	CTL-CPM-A	PROC-CRG-QREG	Read Q1-16 to WL1-16	33	Low
RQC	CTL-CPM-B	PROC-CRG-QREG	Read Channel bus into Q register	n/a	Low
RRPA	CTL-CPM-A	MEM-INT	Read address of highest priority interrupt requested.	34	Low
RSB	CTL-CPM-B	MEM-ADR-BNK	Read Channel 7	n/a	Low
RSC	CTL-CPM-A	CTL-CPM-B	Read central register defined by address in S reg. Bits 1-16 to WL1-16.	35	Low
RSCT	CTL-CPM-A	MEM-CTR-CNT	Read address of highest priority counter request.	36	Low
RSM3	CTL-CPM-A	CTL-CPM-C	Subsequence RSM3 is active. (output to C only, not outside CPM)	n/a	Low
RSTRT	CTL-CPM-A, CTL-CPM-C	PROC-ALU	Octal 04000 to WL's. Block 2 start address.	37	Low
RSTSTG	CTL-CPM-A, CTL-CPM-C	CTL-SEQ	Reset the stage counter to zero.	38	Low
RU	CTL-CPM-A	PROC-ALU	Read U1-16 to WL1-16	39	Low
runPINC	MEM-CTR-CNT	CTL-CPM-C	Run the PINC sub-seq.	n/a	Low
RUS	CTL-CPM-A	PROC-ALU	Read U1-14 to WL1-14 & U15 to WL15,16	40	Low
RZ	CTL-CPM-A, CTL-CPM-B	PROC-CRG-ZREG	Read Z1-16 to WL1-16	41	Low
SBWG	CTL-CPM-C	MEM-EFM, MEM-MBF-MBL	Write G register to memory shifted.	n/a	Low
SNI	CTL-SEQ	CTL-CPM-C, CTL-TPG	Set up for next instruction.	n/a	Low
STBY	CTL-TPG	Various	Put AGC in standby by; disable display,	n/a	Low
ST1	CTL-CPM-A	CTL-SEQ	Set Stage 1 flip flop to 1 at next TP12.	42	Low
ST2	CTL-CPM-A, CTL-CPM-B	CTL-SEQ	Set Stage 2 flip flop to 1 at next TP12.	43	Low
STAGE	CTL-CPM-A	CTL-SEQ, CTL-CPM-C, CTL-SEQ	Execute next sub-instruction as defined by stage counter.	44	Low
TL15	CTL-CPM-A	CTL-SEQ	Copy L15 into BR1.	45	Low
TM3RUPT	MEM-CTR-CTL	MEM-INT	Interrupt 3 asserted	n/a	Low
TM4RUPT	MEM-CTR-CTL	MEM-INT	Interrupt 4 asserted	n/a	Low
TMZ	CTL-CPM-A	CTL-SEQ	Test WL1-16 for all ones. Set BR2=1 if true, else BR2=0.	46	Low
TOV	CTL-CPM-A	CTL-SEQ	Test for overflow (WL16,15). Set BR1/BR2 to 00 if no overflow, 01 if positive overflow, 10 if negative overflow.	47	Low
TP	MEM-EFM	MEM-PAR	Test Parity	n/a	Low
TPZG	CTL-CPM-A	CTL-SEQ	Test content of G for +0. If true, set BR2 to 1, else BR2=0.	48	Low
TRSM	CTL-CPM-A	CTL-SEQ	Test for resume address (0017) during NDX0. If exists, set c(ST)=3 to execute RSM3, else set c(ST)=1.	49	Low
TSGN	CTL-CPM-A	CTL-SEQ	Test Sign. Copy WL16 to BR1.	50	Low
TSGN2	CTL-CPM-A	CTL-SEQ	Test Sign 2. Copy WL16 to BR2.	51	Low
TSGU	CTL-CPM-A	CTL-SEQ	Test sign of Sum (U16). Copy U16 into BR1.	52	Low
U16	PROC-ALU	PROC-CRG-AREG	U reg bit 16 value	n/a	Bit
U2BBK	Only used by FETCH1, not implemented.	N/A	Adder bits U16,14-11 to FB and U1-3 to EB1-3. May be inhibited by signal MONWBK.	53	Low
W20	CTL-CPM-B	MEM-MBF-MBL, MEM-MBF-SFT	Perform CYR	n/a	Low
W21	CTL-CPM-B	MEM-MBF-MBL, MEM-MBF-SFT	Perform SR	n/a	Low
W22	CTL-CPM-B	MEM-MBF-MBL, MEM-MBF-SFT	Perform CYL	n/a	Low
W23	CTL-CPM-B	MEM-MBF-MBL, MEM-MBF-SFT	Perform EDOP	n/a	Low
WA	CTL-CPM-A	PROC-CRG-AREG	Clear and write WL1-16 into A1-16.	54	Low
WALS	CTL-CPM-A	PROC-CRG-AREG, PROC-CRG-LREG	Clear and write into A1-14 from WL3-16. If G1=0, then G16 to A15,16, else U16 to A15,16. Clear and write WL1-2 to L13-14.	55	Low
WB	CTL-CPM-A	PROC-ALU	Clear and write from WL1-16 into B1-16.	56	Low
WBB	CTL-CPM-B	MEM-ADR-BNK	Write to both banks	n/a	Low
WCH	CTL-CPM-A	CTL-CPM-B, PROC-CRG-WCHN	Clear and write W1-14,16,parity into channel bits 1-14,16,parity. Channel address in S reg. Channels 1 & 2 same as WL & WQ.	57	Low
WE	CTL-CPM-C	MEM-EFM, MEM-MBF-MBL	Write G register contents into memory based on S address.	n/a	Low
WEB	CTL-CPM-B	MEM-ADR-BNK	Write to Erasable Bank	n/a	Low
WFB	CTL-CPM-B	MEM-ADR-BNK	Write to Fixed Bank	n/a	Low
WG	CTL-CPM-A	MEM-MBF-SFT, CTL-CPM-B	Clear and write WL1-16 into G1-16 except for addresses 020-023 which causes editing.	58	Low
WL	CTL-CPM-A	PROC-CRG-LREG	Clear and write WL1-16 into L1-16.	59	Low
WLC	CTL-CPM-B	PROC-CRG-LREG	Write L register to channel bus	n/a	Low
WOVR	CTL-CPM-A	MEM-CTR-CTL	Test WL15,16 for positive overflow. If S contains 0025, increment counter 024. If S contains 026, 027 or 030 then execute RUPT.	60	Low
WPCTR	CTL-CPM-C	MEM-CTR-CNT	Increment counter	n/a	Low
WQ	CTL-CPM-A	PROC-CRG-QREG	Clear and write WL1-16 into Q1-16.	61	Low
WQC	CTL-CPM-B	PROC-CRG-QREG	Write to Q register to channel bus	n/a	Low
WS	CTL-CPM-A	MEM-ADR-S, CTL-CPM-C	Clear and write WL1-12 into preS1-12.	62	Low
WSB	CTL-CPM-B	MEM-ADR-BNK	Write to Channel 7	n/a	Low
WSC	CTL-CPM-A	CTL-CPM-B	Clear and write into central register specified by S register	63	Low
WST	CTL-CPM-C	MEM-ADR-S	Move preS data to S reg	n/a	Low
WSQ	CTL-CPM-A, CTL-CPM-C	CTL-SEQ	Clear and write WL10-14,16 into SQ10-14,16 and copy extend flop flop into SQ15.	64	Low
WY	CTL-CPM-A	PROC-ALU	Clear X, Y & CI. Write WL1-16 into Y1-16.	65	Low
WY12	CTL-CPM-A	PROC-ALU	Clear X, Y & CI. Write WL1-12 into Y1-12.	66	Low
WYD	CTL-CPM-A	PROC-ALU	Clear X, Y & CI. Write WL1-14 into Y2-15 and WL16 into Y16. Write WL16 into Y1 except 1) when end-around carry is inhibited by NEACON 2) during SHINC sequence or 3) PIFL is active and L15=1.	67	Low
WZ	CTL-CPM-A, CTL-CPM-C	PROC-CRG-ZREG	Clear and write WL1-16 into Z1-16.	68	Low
Z15	CTL-CPM-A	PROC-CRG-ZREG	Set bit 15 of Z to 1.	69	Low
Z16	CTL-CPM-A	PROC-CRG-ZREG	Set bit 16 of Z to 1.	70	Low
ZAP	CTL-CPM-A	CTL-CPM-A	Generate control pulses RU, G2LS & WALS. Used by MP K instruction.	71	Low
ZIP	CTL-CPM-A	CTL-CPM-A	Generate control pulses A2X & L2GD. Also the pulses shown below.	72	Low

ZIP also implies if L15,2,1 are:

L15	L2	L1	READ	WRITE	CARRY	REMAINDER
0	0	0	–	WY	–	–
0	0	1	RB	WY	–	–
0	1	0	RB	WYD	–	–
0	1	1	RC	WY	CI	MCRO
1	0	0	RB	WY	–	–
1	0	1	RB	WYD	–	–
1	1	0	RC	WY	CI	MCRO
1	1	1	–	WY	–	MCRO

The instructions that are executed by the AGC are integral to the understanding of both the hardware and the software. They are described here so as not to clutter the design section. In the following sections, L is the location of the instruction and K is the data address (i.e. the operand) of the instruction. Items in parenthesis preceded by “c” mean the resulting contents of that variable. Items in parenthesis preceded by “b” mean the contents before the operations. The “editing if K is 0020 – 0023” means the bit shifts and rotates occur.

There are both “voluntary” and “involuntary” instructions. The voluntary instructions are the ones that can be coded, compiled and placed in fixed memory to execute. The involuntary instructions are triggered as part of counter interrupts and cannot be coded into a fixed memory program. The only involuntary instruction implemented here is the PINC instruction due to the limited counters implemented.

1. TC K: Transfer Control

This instruction transfers control to address K after placing the return address into Q. The special cases are K = 3, 4 & 6.

c(Q) ← L + 1

1. TC 3: RELINT: Allow Interrupts

This instruction allows the resumption of interrupts after the INHINT instruction.

1. TC 4: INHINT: Inhibit Interrupts

This instruction inhibits interrupts from occurring.

1. TC 6: EXTEND: Extracode Bit

This instruction sets the extracode bit which sets the high order, bit 16 of the opcode. This is used to double the number of available instructions and is used for less frequently used instructions as it requires this extra instruction to execute the extracode instructions.

1. CCS K: Count, Compare & Skip

This instruction is a four way branching instruction. The following describes the four branching conditions. The value assigned to K is called the Diminished Absolute Value (DABS) which replaces A with one less than the its previous value. This allows for a looping count down construct.

c(A) ← DABS[(K)] where DABS(x) = |x| - 1 if |x| > 1 or +0 if |x| <= 1

c(K) ← b(K), editing if K is 0020 - 0023

if b(K) > +0 then no skip

if b(K) = +0 then skip to L + 2

if b(K) < -0 then skip to L + 3

if b(K) = -0 then skip to L + 4

1. DAS K: Double Add to Storage

This instruction adds the contents of K and K + 1 to the A and L registers. If K or K + 1 is 0020 through 0023 then the shifts/rotates occur.

c(K, K + 1) ← b(A, L) + b(K, K + 1)

1. LXCH K: Exchange L and K

This instruction exchanges L with K. The prime tick indicates overflow correction.

c(L) ← b'(K)

c(K) ← b(L), editing if K is 0020 - 0023

1. INCR K: Increment

This instruction increments K.

c(K) ← b(K) + 1, editing if K is 0020 - 0023

1. ADS K: Add to Storage

This instruction adds A to K and the results are both placed into A and K.

c(A) & c(K) ← b(K) + b(A), editing if K is 0020 - 0023

1. CA K: Clear and Add

This instruction places the value of K into A.

c(A) ← b(K)

c(K) ← b(K), editing if K is 0020 – 0023

1. CS K: Clear and Subtract

This instruction places the negated value of K into register A.

c(A) ← -b(K)

c(K) ← b(K), editing if K is 0020 - 0023

1. INDEX K: Index Next Instruction

This instruction modifies the next instruction by adding the operand to the next instruction.

c(K) ← b(K), editing if K is 0020 – 0023

Use [b(K) + c(I + 1)] as next instruction

1. INDEX 0017: Resume Interrupted Program

This is a special instruction that resumes from an interrupted program. c(0017) contains the next instruction.

c(Z) = c(0015)

1. DXCH K: Double Exchange

This instruction exchanges the contents of A and L with K and K + 1.

c(A, L) ← b(K, K + 1)

c(K, K + 1) ← b(A, L), editing if K or K + 1 is 0020 - 0023

1. TS K: Transfer to Storage

This instruction transfers the contents of K to storage.

c(K) ← b(A), editing if K is 0020 - 0023

if (A) has positive overflow, A ← +1, skip to L + 2

if (A) has negative overflow, A ← -1, skip to L + 2

1. XCH K: Exchange

This instruction exchanges the data in K with the data in register A.

c(A) ← b(K)

c(K) ← b(A), editing if K is 0020 - 0023

1. MASK K: Mask

This instruction ORs the contents of K with the contents of A.

c(A) ← b(A) || c(K)

1. READ KC: Read Channel KC

This instruction reads the KC channel into register A.

c(A) ← c(KC)

1. WRITE KC: Write Channel KC

This instruction writes the contents of register A onto the KC channel.

c(KC) ← c(A)

1. RAND KC: Read and Mask

This instruction reads the KC channel and ANDs it with the contents of register A.

c(A) ← b(A) & c(KC)

1. WAND KC: Write and Mask

This instruction writes the contents of register A masked with the contents of KC channel into A and KC.

c(KC) and c(A) ← b(A) & b(KC)

1. ROR KC: Read and Superimpose

This instruction reads the KC channel and ORes it with the contents of register A.

c(A) ← b(A) || c(KC)

1. WOR KC: Write and Superimpose

This instruction writes the contents of register A ORed with the contents of KC channel into A and KC.

c(KC) and c(A) ← b(A) || b(KC)

1. RXOR KC: Read and Invert

This instruction reads the KC channel and XORes it with the contents of register A.

c(A) ← b(A) xor c(KC)

1. DV K: Divide

This instruction divides the contents of A by the contents of K. The quotient is placed in A and the remainder is places in Q.

c(A) ← b(A, L) / c(K)

c(L) ← remainder

1. **BZF K: Branch Zero to Fixed ** This instruction branches to instruction in K if the contents of A is zero else it simply executes the next instruction.

If c(A) = 0 then branch to K.

1. MSU K: Modular Subtract

This instruction performs a 1's compliment subtraction of K from A. A modular subtraction is the difference between two unsigned 2's compliment inputs.

c(A) ← b(A) 0 b(K) where 0 is a modular subtract

c(K) ← b(K), editing if K is 0020 – 0023

1. QXCH K: Exchange Q and K

This instruction exchanges the contents of the Q register and the contents of K.

c(Q) ← b(K)

c(K) ← b(Q), editing if K is 0020 – 0023

1. AUG K: Augment

This instruction augments K which means the value is incremented if positive or decremented if negative.

If b(K) >= +0, c(K) ← b(K) + 1, editing if K is 0020 – 0023

If b(K) <= -0, c(K) ← b(K) - 1, editing if K is 0020 – 0023

1. DIM K: Diminish

This instruction diminishes K which means the value is decremented if positive or incremented if negative.

If b(K) > +0, c(K) ← b(K) - 1, editing if K is 0020 – 0023

if b(K) = 0, c(K) ← b(K), editing if K is 0020 - 0023

If b(K) < -0, c(K) ← b(K) +1, editing if K is 0020 – 0023

1. DCA K: Double Clear and Add

This instruction moves K and K + 1 to A and L.

c(A, L) ← b(K, K + 1)

c(K) ← b(K), editing if K is 0020 – 0023

c(K + 1) ← b(K + 1), editing if K is 0020 – 0023

1. DCS K: Double Clear and Subtract

This instruction moves the negated values of K and K + 1 to A and L.

c(A, L) ← -b(K, K + 1)

c(K) ← b(K), editing if K is 0020 – 0023

c(K + 1) ← b(K + 1), editing if K is 0020 – 0023

1. INDEX K: Index Extracode

This instruction is the same as the non-extracode version except the extracode switch is not reset.

1. SU K: Subtract

This instruction subtracts the contents of K from A. If an overflow occurs, either +1 or -1 is placed into A depending on the type of overflow.

c(A) ← b(A) – b(K)

c(K) ← b(K), editing if K is 0020 – 0022

1. BZMF K: Branch Zero or Minus to Fixed

This instruction branches to the instruction at K if register A is zero or negative, otherwise it continues with the next instruction.

if c(A) <= +0, branch to instruction at K,

else execute next instruction

1. MP K: Multiply

This instruction multiplies the contents of with the contents of K. The results are placed into the A and L registers.

c(A, L) ← b(A) * c(K)

1. PINC: Positive Increment

This involuntary instruction is used to increment a counter by one.

c(CTR) = b(CTR) + 1