The basics of the protocol are simple.

It is a symmetric, point-to-point full-duplex protocol with 2 binary signals per direction.

Each peer needs 2 output pins and 2 input pins, no direction reversal, so each pair of wires can be dedicated and designed easily, with much fewer analog tricks.

Signaling uses "transition" encoding, and since there are 2 wires, 4 symbols, only 3 values can be transmitted, let's call them "trits".

Each trit is built from the XOR of the previous line value, sampled exactly at the same time in the pair.

•  For example, to send a trit to a pair of GPIOs, one takes the previous output state and XORs the trit before sending the new value to the GPIO.
• To receive a trit, sample both GPIO pins at the same time, and XOR the new value with the previous value => you get a trit.

Encoding is simple :

00 => idle / no trit
01 => encode bit 0
10 => encode bit 1
11 => ACK / end of frame

One should be careful to not swap the wires but this has the benefit that a "receive-only" peer can save one wire, by sending one bit only and the value is cloned/duplicated to emulate a full-duplex device. So the protocol can work with 3 wires in certain cases.

Self-clocking works with the simple ping-pong idea : One peer sends a trit, and waits for the peer's trit in return. No crazy encoding is performed with base-3 values : the 3rd value is an "end of frame" that eases decoding and framing. This also double as an ACK signal when the peer has no data to send. Since ACK is encoded as 11, the 3-wire configuration is possible.

Also, binary transmission consumes half the energy because there is only 1 transition instead of 2 for ACK. But ACK can be delayed during idle periods.

Each peer announces its availability on the link by sending ACKs periodically, like 1 per second. Link is "established" if a ACK is received within 1 second or so, to let the peer "wake up" for example. So the slowest speed is 1 baud. Highest speeds might be in the MHz range, depending on the link's length, drive, signal edges/slopes, circuit/SW latency...