This board includes:
- ADC with input amplifier
- some power supplies
- simple graphics controller for LCD implemented in FPGA
- signal processing implemented in FPGA: conversion to baseband, filtering, downsampling, RMS calculations
- microcontroller which controls the whole system, does calculations on the results from FPGA, controls keyboard and display.
Design documentation is attached (see "Files")
Files
Digital_design_pack.zip
design files and description of digital part of spectrum analyzer
First the signal is multiplied by 3MHz sin and cos digitally, then FIR filtering with simultaneous dropping samples for decimation (both I and Q signals). After one or more filtering/decimation stages, RMS is calculated from remaining samples - that's all. About 120 taps (probably the filter is currently too good for the hardware so it's just some initial value to be tuned later).
Are you using only FIR filters before each decimate by 10 stage? How many taps?