I know that the weakest part is currently my 1st LO so I tried to check what will happen if I replace it with a better synthesizer. I used temporarily STuW81300 which is single chip synthesizer with integrated VCO. It improved results noticeably. All random spikes disappeared from displayed spectrum and it was possible to achieve resolution down to about 1kHz.
STuW81300 on 1st picture (resolution down to 1kHz), my synthesizer on 2nd picture (no comment):
I also discovered that there are some unexpected frequencies about 30kHz away from the measured frequency. I couldn't figure out where they come from. I tried many changes: different power supply (linear instead of switching), changing LCD clock, slightly tuning main oscillator, tests at different input frequencies, different source of signal, different 2nd LO, different 1st LO (I couldn't sweep from microcontroller so I was sweeping it manually while observing level), removed input attenuator module different 5V for 1st IF amplifier. All the time there was some 30kHz modulation. When I provided 2nd IF (228MHz) signal from professional synthesizer to input of IF board and swept manually I didn't notice anything 30kHz away from center frequency so it seems that the 30kHz adds somewhere in 1st and 2nd mixers board. UPDATE: I think I found that - my signal generator (nanoVNA v2) generated the modulation or jitter and and also 2nd LO generated similar modulation or jitter. So as long as I tried to change one thing every time I saw the same effect but from different sources. Conclusion: use different source instead of nanoVNA v2 and improve 2nd LO.
I did some testing to see where noise on IF board comes from. It seems that IF amplifier makes the noise (of course, 1st stage is critical). When the board is shielded, there's not much difference if I completely disconnect input of the amplifier. Maybe some changes of amplifier circuit will help but I don't expect that big improvement is possible. Improving IF filters to loose less signal may be more effective.
The design is most likely overcomplicated, considering availability of off-the-shelf components which can replace most of the work. My goal is to learn play with RF, practical usability of the project is not a major concern.
The architecture in a few words is as follows: - the input signal 0-3GHz is upconverted to first 4GHz IF - the signal is downconverted in a few steps: 228MHz, 28MHz, 3MHz - the final analog 3MHz is converted by ADC and further processed by FPGA - the FPGA mixes the signal with sine and cosine and moves the spectrum down to baseband complex signal, then filters and downsamples the signal (one or more times, depending of selected resolution bandwidth), finally RMS is calculated from the filtered signal
A few words about why it doesn't work:
- The biggest issue is really bad 1st LO. It's a wideband 4-7GHz synthesizer, quite hard to make. It has VCOs up to 3.5GHz so the frequency must be doubled. This creates need for adding switched filter banks. The filters and switches are quite bad and introduce a lot of loss, which is then compensated by a lot of gain. The result is that the small signal is spoiled by noises from ambient and also the amplifier with huge gain tends to be unstable. And the whole board is not shielded yet. Bad quality of the 1st LO creates a lot of random spurs in the measurement.
- IF part which converts signal from 228MHz to 3MHz contains filters and mixers which adds some losses, then IF amplifier introduces noise. The overall SNR seems too high. Filters should be higher quality (maybe still with air coils but larger), amplifiers may need to be somehow optimized, also some filtering at the end may help to cut off more low frequency noises. So the IF part works but it's not great.
- First and second mixers - this part is probably not great but it's probably not the biggest problem (may need more testing but possibly it's good enough for now).
- Digital part - it works but may need some optimization, improvements, debugging.
Rather than using a 3 MHz IF, consider a 5 MHz IF into the ADC that is running at 20 MSPS. This simplifies the conversion to baseband IQ because the sine and cosine lookup values for 5 MHz will reduce to a stream of +/-1's and 0's. The first four samples for sine(2pi*5MHz*n/20 MHz): 0, 1, 0, -1 and cosine(2pi*5MHz*n/20MHz) : 1, 0, -1, 0. This pattern repeats after the first four samples.
Eliminating the error and overhead from using sine and cosine lookup tables is the primary reason why digital IF designs aim to center the analog signal at Fs/4 for simple low pass sampling, where Fs is the ADC sample rate. Edit: The need for multiplication is also eliminated, which speeds up processing if done in software or reduces the required number of hardware multipliers if done in a FPGA.
Taking advantage of aliasing, "undersampling" or "bandpass sampling" can be used to eliminate the need for an additional downconversion of the analog signal. In that case, the IF should be centered at (n +/- 0.25)*Fs, for n = 0, 1, 2, etc..
It might be possible in your design to change your third IF frequency to 25 or 35 MHz and just sample it with the ADC at 20 MSPS. Depending on the nyquist zone bandwidth (=Fs/2), center frequency and desired bandwidth, the filter requirements and technology (SAW, crystal, LC, etc) tradeoffs need to be considered for feasibility and cost.
Thanks for the hints, after finishing next version of 1stLO I'll probably make redesign of the IF board with other LOs so I'll be able to maybe rearrange some IFs. I'm afraid that sampling with 20MSPS using 20MSPS ADC can distort signal because of analog part of ADC liimitations but maybe still worth upgrading ADC to simplify the design. And I guess I'll need some additional digital filter after using sampling for downconversion.
I'm not sure if I completely understand what you mean by "sampling with 20MSPS using 20MSPS ADC". Are you referring to concerns with ADC distortion when the ADC at its maximum sampling rate specification? Which part are you using?
I mean that ADCs sample and hold circuits are probably designed with assumption that input frequency won't exceed 0.5 of max sampling. If I exceed nyquist then probably I'd need to test or prove that analog part is still ok in that conditions. I use AD9235BRUZ-20 (I could change to higher speed variant -40).
Good luck with it. You are well along, so a bit late for my suggestions, but anyway...
I considered the GPS 1575MHz for the first IF. GPS Saw filters are very cheap and common. Also GPS is a protected band, so there should not be strong local transmitters in band there.
If you look at the transfer function of some you see two things:
- They are a lot wider than 2MHz (some are wider again to include glonass I think), but narrower than most other microwave filters
- they have strong nulls either side. You should be able to put your 2nd IF image into one of the nulls.
This seems to be suggest 2nd IF in the 25-50MHz range dependent on the filter.
If you used an LC 2nd IF you could just tune it to the best null region.
If you look more closely, you see you could put your IF at the edge of the filter. Now it might just be possible to have a 10.7MHz 2nd IF, opening up a wide range of standard ceramic and crystal filters for the 2nd IF. h
(Temperature sensitivity of the SAW filter, and especially the nulls may be a big issue with a 10.7 IF)
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I thought it would be nice to use the nanovna V2 as the basis of a very basic 0-1G spec an, by splitting off the rx mixer output high side to a GPS filter and thence the IF strip.
Good choice of IF frequencies and filters will help you a lot. Making and tuning custom filters in my design requires a lot of manual work so it's probably mostly not a good choice. There are some advantages, eg. I can choose my input frequency range as I want, choosing final analog IF at 3MHz allows to have the widest RBW 1MHz while using still relatively cheap ADC (20MSps), 2nd and 3rd IF are made by easy to use digital ICs.
Rather than using a 3 MHz IF, consider a 5 MHz IF into the ADC that is running at 20 MSPS. This simplifies the conversion to baseband IQ because the sine and cosine lookup values for 5 MHz will reduce to a stream of +/-1's and 0's. The first four samples for sine(2pi*5MHz*n/20 MHz): 0, 1, 0, -1 and cosine(2pi*5MHz*n/20MHz) : 1, 0, -1, 0. This pattern repeats after the first four samples.
Eliminating the error and overhead from using sine and cosine lookup tables is the primary reason why digital IF designs aim to center the analog signal at Fs/4 for simple low pass sampling, where Fs is the ADC sample rate. Edit: The need for multiplication is also eliminated, which speeds up processing if done in software or reduces the required number of hardware multipliers if done in a FPGA.
Taking advantage of aliasing, "undersampling" or "bandpass sampling" can be used to eliminate the need for an additional downconversion of the analog signal. In that case, the IF should be centered at (n +/- 0.25)*Fs, for n = 0, 1, 2, etc..
It might be possible in your design to change your third IF frequency to 25 or 35 MHz and just sample it with the ADC at 20 MSPS. Depending on the nyquist zone bandwidth (=Fs/2), center frequency and desired bandwidth, the filter requirements and technology (SAW, crystal, LC, etc) tradeoffs need to be considered for feasibility and cost.