PD32 V1.0 Gerbers.zip

Gerber files for manufacturing

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PD32-schematic.pdf

schematic

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PD32-PCB.pdf

PCB layout

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PD32-FRONT.jpg

3D render front PCB

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PD32-BACK.jpg

3D render back PCB

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PD32.csv

simple BOM

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Keystone PC AT board bracket model 9202 -- datasheet 202-743470.pdf

The proposed PD32 board uses the Keystone model 9202 bracket to mount in the target system

https://www.mouser.com/ProductDetail/Keystone-Electronics/9202?qs=g5fiFmky%2Fl4bFM8ICVGfOQ%3D%3D

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NS_DP84412_logic-equations.txt

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PD32-bom.zip

Interactive BOM (requires browser such as Chrome)

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rom.a32.txt

Boot ROM source code in 32K assembler.

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dram.pal.txt

The logic equations for the PAL that works with the DRAM controller.

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lhu646.pal.txt

This pal generates all the control signals for the 74AS646 data flow latch as well as the CWAIT (for PD32) and IWAIT (for the host) syncronisation signals. The CLK signal is used to clock the data flow flip flop. The GATE signal enables the output of the 74AS646 (the direction comes from a separate ic).
The IDO signal is a single status bit that the host can read to determine whether any data is left in the 74AS646 (regardless of direction) or the state of the PD32 service request flip flop.

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646a.pal.txt

This pal generates the control clock signals for the 74LS646 transceivers.
Depending on the status of the two flip flops, the pal generates the clock signal for the appropriate 74LS646.
The pal also generates CWAIT (for the 32032) if either of the 74LS646's are empty on a read or full on a write.

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dec32.pal.txt

This pal performs the decoding for the 32016 memory space. The signal 'SWAP' is used to select either EPROM or RAM at low memory. At power on or after a reset EPROM is selected at low memory. The EPROM contains the necessary bootstrap software to communicate with the host system (pc).
Note: Since the interface is a fairly generic 8 bit parallel port, any system (not just the PC) can become the host for the 32016.

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