DigSim is a python based framework for digital circuit simulation. The main purpose of the software is to, in an educational way, play around with digital logic (simple gates and verilog designs).

When working with block design in Verilog/VHDL the simulation tools are normally fed with test stimuli (a very non-interactive way of working...) A block design can be synthesized and tested on an FPGA (where there are possibilities for interactivity if buttons and LED/Hexdigits are available), but that often has a great cost in time (and sometimes money) leading to long turnaround time.

I started developing DigSim to make it easy to implement and visualize the functionality of simple verlog modules. During development I tried to synthesize larger verilog designs, such as the classic 6502 CPU, and even if it is slower than many other simulators it is not entirely useless.