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16 Bit CPU in Verilog HDL

A very minimal pedagogical 16 bit processor based on the Harvard Architecture

talhatalha
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pc.v

v - 682.00 bytes - 09/13/2023 at 14:26

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README.md

md - 236.00 bytes - 09/13/2023 at 14:26

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topmodule.v

v - 1.22 kB - 09/13/2023 at 14:26

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register file.v

v - 1.21 kB - 09/13/2023 at 14:26

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instruction memory.v

v - 1.17 kB - 09/13/2023 at 14:26

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