SSP25 Digital Signal Processor

The SSP25 provides STEbus systems designers with a powerful digital signal processing capability which can act as a slave in a STEbus system to handle computation-intensive tasks such as frequency/vibration analysis or event counting.

Based on a TMS320C25 CPU, a 16-bit 40MHz device offering 10 MIPS performance, the board implements the high performance Harvard Architecture with its separate program and data spaces, and is fitted with 32K words static RAM divided equally between the two; 4Kbytes of each space is dual-ported to the STEbus. The DSP chip itself provides 544 words of internal RAM to optimise performance.

Twenty four I/O lines, 16 inputs or outputs and 8 inputs, are provided via the Signal Conditioning Bus interface. Three TMS320C25 interrupt lines, and the device's serial channel (for connection of specialised peripherals such as DSP-oriented A/D converters) are also brought out via this connector. The TMS320C25 may optionally be either interrupted or reset via the STEbus by writing into I/O space locations.

Software: Support includes a macro assembler, 'C', linker and simulator running on an Arcom STEbus PC.

Interface

The board implements a slave interface as a 16-bit message port which can be link-selected to reside anywhere in the 4Kbytes I/O space.

Power consumption:

Typ 700mA @ 5 V

Ordering Information:

SSP25       40 MHz DSP board
SSP25-50    50 MHz DSP board

Features

• 16-bit 10 MIPS DSP slave
• 32K words SRAM
• 24 I/O lines
• Available with either a 40 MHz or 50 MHz CPU
• Signal Conditioning Bus interface