The project https://github.com/YannGuidon/miniMAC_tx got tape-out-ed on ihp26a but the design is bork and could at best over-scramble noise...

Then I tried my luck again with https://github.com/ygdes/miniMAC_5L on IHP 0p4 and at least the Hammer18 circuits work as intended, but the gPEAC18 resisted again and didn't make it.

gPEAC is indeed a very delicate piece of circuit and the VHDL took ages to get right. I have the C reference code, the VHDL RTL but the Verilog structural gate-mapped version wouldn't work. Something somewhere is always working wrong, the debugging is excruciating (cumbersome and slowwww), Verilog is a PITA and the VHDL variables (in the RTL code) are not exposed to gtkwave, so it's impossible to compare with the Verilog version where all wires are visible signals.

Today, the Verilog code for gPEAC is complete but fails to comply with the C and VHDL code. And I see no sane and reliable way to find what is wrong. So I'm forced to rebuild the WHOLE thing from scratch.

The plan is to redesign everything simultaneously, starting from the simplest circuit and adding new circuits little by little, in four versions:

• C reference
• VHDL RTL
• Schematic with precise annotations
• Verilog gates

To get from the current state to a smaller, easily testable circuit, both the encoder and decoder must be cut down:

• The B pipeline must be cut from the A, the Y removed from X.
• The pipelines get reduced to one cycle

then it's rather easy to rebuild from scratch...

Fortunately 135. Number comparison with the iHP PDK does not need to change.

(update : well ok it did, a minor tweak)