It just occurred to me a minute ago that the F1 and F0 flags do not count toward the parity so they could be altered...

Of course, the subsequent PEAC scrambler would easily notice all the bits being flipped but would not figure where it happened.

So it's just a matter of routing another XOR gate.

The VHDL code already detects "too many zeroes" thanks to the same popcount unit as in the encoder.

New circuit:

This adds a bit more latency too, but it's still comparable to the PEAC stage, as a few gates could be moved before/after the DFF stage.

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Note : the extra XOR are not defined in the parpop8 sub-unit because the "ternary rotation" must choose by itself where the FA comes from, depending on its location (receiver or transmitter). The VHDL code shows how it's done, it's a subtle swap but it works well.

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VHDL code there : parpop_20250325.tgz