This project originally was meant to be a simple, standalone circuit but now the system contains 3 modules :

• miniMAC (here, doing the high-level packet protocol)
• #miniPHY 
• miniAFE (to be done)

It is modular and provides some sort of plug-in replacement/evolution, but mostly it decouples the development so I can work on all 3 aspects in parallel.

The interfaces are :

• Host CPU memory-like access to the control/status registers and the packet buffer (onchip)
• MAC-PHY link : one or two 2×4bit full-duplex + QSDE signals, depending on physical configuration (onchip or offchip, tbd)
• Physical link to AFE : 4 pins per pair (tri-level, 2 in 2 out), so 8 or 16 pins. Some pins can be used for configuration sensing with weak pull-ups or pull-downs.
• AFE is connected to a Fast or Gigabit Ethernet magjack, with 2 or 4 pairs.

I have removed the "asymmetrical" configuration for 4 pairs, as it makes it uselessly complex.

But there is still no autosense of each pair's direction. Some inversion will have to be done at the socket level, probably mechanically. Since cables won't be changed often, it's possible that the AFE-Jack modules can be interchangeable and swapped from one end of the cable to the other. Hence the need for standardisation too : the AFE must plug everywhere.

Or I find a way to swap the jack's polarity, mechanically, such that all the Cat5 cables are "straight".