There is a little tiny detail that makes the last log Unit swap difficult to implement: the transmitted data must contain all the bits generated by the scrambler, not just the data bits. This was more or less inherent (and hidden) with PEAC16 because the modulus was the same size as the data.

With gPEAC it's not so anymore. The modulus is 18 bits, one more bit than the encoded data. And it must be transmitted. This reduces the "extra parity" to only 2 bits and makes the error detection less efficient, requiring more words to reach a 1E6 confidence level.

But this is an unavoidable constraint, otherwise the system can't work. And the "extra bit" also provides some protection as well, directly or indirectly, since flipping could lead to a forbidden value (outside of the modulus) which can be detected during the mod operation. The probability depends on the modulus though.

Overall we end up with:

• 16 data bits
• 1 C/D bit
• 1 "modulus" bit (with a probability of 1 lower than 50%)
• 2 parity bits for faster detection and reduced buffer size.

All we can do is before and after this stage.

• "Before" is relatively easy: it amounts to computing two parity bits, in parallel with the gPEAC. The revised version checks the input data (16 bits) and the Y register (18 bits). The 34 bits are interleaved to spread the parity evenly across the 2 bits. The X register is part of the state of the scrambler but not readily available for the descrambler.
• "After" is again the 3-sections Gray parity circuit, that takes 17 bits and generates 3 more parities, XOR-mixed with the M and P0/P1 bits. Or (maybe better), the M/P0/P1 bits could be used as the "solid" bits in this codec. There is no need for more interleaving before and after since the Nibble interleave already does a good job on the link side, and the gPEAC side has no "tropism" towards a given bit (previously, it was about the MSB of PEAC but this is replaced with a more general parity).

This is relatively simple but this lengthens the pipeline and latency of error detection, now 3 cycles:

• de-Gray (some XORs deep)
• gPEAC subtraction (2 cycles)
• parity of output data and Y, and comparison

3 cycles is 60 bits and I don't even count the PHY overhead. But this is worst case and is not necessarily pipelined if the bandwidth is slow enough.

The compromise is justified though : it may take 3 words to start detecting an error but then the rate of detection is much higher. I also got rid of the weird "parity combination" and a lot of awkward wire permutations. This also preserves the 2-word signalling protocol since the data/payload itself can hold more extra bits for checking.

Which brings me to an extension of the protocol with control words...

...............

Update :

the post-Gray decoder needs the interleaving to match the latency of subtractor's logic depth.

So the architecture is mostly like before, and the Vs are folded to follow the gPEAC's carry chain. The gPEAC can be built around three Radix-6 Carry Lookahead Adder blocks.

This "shaves" a few logic gates of latency and merges the first two (pipeline/logic) stages. Alternatively, the de-Graying can also be computed during the nibble unshuffling. But integrating the de-Graying with the subtractor might offer some opportunities for optimisation of the several XORs.

As a consequence: the m/p/p bits are XORed with the partial parities later/in parallel.