The new results are in and clearly superior, with little effort!

• Here, only one bit is flipped, as it's the worst case.
• The initial peak is identical
• The number of remaining undetected errors is almost cut in half (17% vs 31%) => woozah !
• The "dip" at the 2nd cycle is gone.
• cycles 4 to 32 : NRZI is about 20% better.

Get the source code at gPEAC18_VHDL.20251220.tbz

I'm already pondering how to increase this performance without adding more DFF.