The recent Success has been resounding but the battle is not totally over.

Remember that the Golden Rule is that the error detection is related only to the density of parity bits, and then the probability is 2^-n. That's it.

There is still a flaw in the test that I have created : it only tests consecutive bit flips within one word, not several words with some bits flipped here and there.

Using several words, there is an easy method to create an error pattern that takes much longer to detect:

• First, flip a bit in the first word, which takes the longest to percolate to one of the PEAC control outputs. This could create a wrong sequence that lasts dozens and dozens of cycles.
• Then, the Hammer circuit is looked up again and again to generate the counter-signal that "masks" the original flipped bit.

This is a blueprint to alter one selected bit and there are 18 sequences, one for each bit position.

But the possible harm (if this is an "aggression") is pretty ... limited.

• It is barely possible to control the state of the PEAC registers. There is no way to know if or when a single flipped bit would avalanche toward the control bits, in the first cycle or any next iteration. It would take "a dozen cycles" in average but it's too dependent on the timing...
• The aggression would affect one, or just a few bits, because otherwise the error would be quickly caught by PEAC. So the potential targets (or attack surface) is low.
• The final cleared double-word blows the whole scheme away.

So the joint use of additive and XOR circuits shows that they protect each other, better than just pure XOR or Add-based solutions. Making up alterations that can last an arbitrary long time is possible but increasingly pointless and the final checksum validates the whole transaction, in case the packet is too short to let the alteration bubble up in the PEAC.

The system could be made even tighter, by routing some of the Hammer's bits and XORing with the PEAC's decoder output. This would foil some attacks but the normal operation would not be better (the few XOR gates would add marginal complexity but the latency would increase).