Nintendo Controllers, CPU Core, and SDRAM

A project log for DE0 Nano FPGA with 15 bit VGA and PPU

DE0 Nano FPGA with 15 bit VGA and Picture Processing Unit.

tehaxor69 • 03/05/2017 at 02:01•0 Comments

Added support for a SNES controller and a N64 controller, the SNES was simple, with the N64, I had to use a 2 MHz nyquist rate sample to work reliably.

Added a simple CPU core, using M9K blocks, and supports 3 instructions so far, "NOP", "INC REG", "DEC REG".

Added a SDRAM controller.

Nintendo Controllers, CPU Core, and SDRAM

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