Draft Bus Layout

Here is a draft bus layout -

 1 +5V   +5V
 2 +12V  +3.3V
 3
 4
 5
 6 } 18 pins for other signals
 7
 8
 9
10
11
12 REFSH RESET
13 M1    CLK
14 INT   NMI
15 BUSRQ BUSAK
16 HALT  WAIT
17 MREQ  IORQ
18 RD    WR
19 A14   A15
20 A12   A13
21 A10   A11
22 A8    A9
23 A6    A7
24 A4    A5
25 A2    A3
26 A0    A1
27 D6    D7
28 D4    D5
29 D2    D3
30 D0    D1
31 GND   GND
32 GND   GND
----------------------
64 Pins Total
56 Pins Signal
 8 Pins Power


38 Pins Z80 bus
18 Pins Other signals


XC9536XL has
44 Pins Total
 6 Pins Power
 4 Pins Programming
34 Pins Signal


Interface 5V CPU to LVTTL Bus
38 Pins Z80
56 Pins Backplane
94 Pins Total Signals


So 3 CPLDs (102 Signals) will interface a Z80 CPU
to the backplane with 8 spare signal pins
One of the spare pins van go to a 50MHz or 100MHz
active crystal oscillator


This will make all but the 8 power pins re-definable

Discussions

K.C. Lee wrote 04/05/2017 at 19:06

You would want some ground or well decoupled power pins right next to the control signals around pins12 - 18. It is important to minimize the loop area around them to reduce cross talks.

You can get away with the Address/Data if you give sufficient time for setting.

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Yann Guidon / YGDES wrote 04/05/2017 at 19:04

typo : "One of the spare pins van go to"

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Yann Guidon / YGDES wrote 04/05/2017 at 19:03

Important advice : at least spread the GND throughout the buses, like 2 GND in the data bus and 4 GND in the address bus, it helps a bit with noise immunity... Works with other "non switching, low impedance" (and decoupled) signals as well such as 3.3V, 5V, 12V

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To {Translate} || to [CPLD]

Signal Level Compatibility

Discussions

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