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Board Fab
10/06/2025 at 02:08 • 0 commentsFabbing the board was easy, I decided to try using a hot plate along side my typical hot air and iron setup. Given the large pours and thermal vias, it made a noticeable difference in some places. I also was able to recycle the larger electrolytic capacitors and the low voltage transformer from the old board using a butane soldiering iron.
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Original Sins... Version 1.0
08/25/2025 at 02:26 • 0 commentsBest intentions can be killed by a poor layout and execution, along with sub-par lab equipment and limited experience.
The Issues:
My original version suffered from multiple issues:
- Generally poor layout (large loop areas on gate drive and FET output runs).
- Multiple footprint errors.
- Lack of space for FET snubber components.
- Ringing on FET Drains (Due to above issues).
As a result, the system always ran at a partial voltage via Variac. In the early years, I blew up a lot of FETs and gate drivers without ever really understanding why... I had assumptions is was due to poor layout and lack of proper bypasses etc. (The reality is the issue was rising edge ringing violating Vds on the FETs, eventually leading to shoot through or gate driver destruction.)
At the time, my 1970's Philips scope lacked good triggering and I lacked experience on how to properly measure a 25-50MHz ringing edge. Two years ago I dug this project back out, with a modern scope and lab hardware, as well as 8 years more experience, the issue was immediately obvious... As was the solution, to add a snubber, unfortunately the power dissipation was getting high, making the idea of keeping the design as it is unrealistic.
Original Board:
Highlighting a few of the issues below, you can quickly see why after all the testing on the original board, it was time for a new one.
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The Ringing:
Using a cutoff coax cable (trick to easily and accurately measure high speed and small signals) you can see the ringing is extreme. The freqency is high which is good, but the amplitude is ~50% of the actual FET voltage, and this is only at 30V of the expected 180V.
The snubber mostly helped, along with slowing the edge rise time via gate resistor. although at elevated voltage, the ringing returned, along with a >2W power dissipation, which given the lack of proper footprint, made this somewhat unsustainable.
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Snubber Design:
For anyone interested in designing a snubber, it is trivial. There are a few ways to calculate the values, all should end up the same. TI has a short app note about it here: TI App
That being said, often people over-calculate the power dissipation. What most tutorials fail to mention is power dissipation is related to the edge speed. Slowing the signals edge helps reduce overall power by a significant margin. I do not have the source for where I found this, but I have found it accurate in my use on flybacks etc.
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Collin Matthews





