• Relaxation Oscillator - Not Oscillating

    Jesse Farrell • 09/15/2025 at 04:37 • 0 comments

    This design uses two clock sources to drive 12x buffers. These clocks don’t need to be particularly accurate or fast, so I used a relaxation oscillator.

    The theory behind a relaxation oscillator (https://www.ti.com/lit/ab/snoa998a/snoa998a.pdf?ts=1757848540517) is very simple. You can make one using 3 parts; a Schmitt trigger inverter, a resistor, and a capacitor as shown below. In this case Vt+ and Vt- are the positive and negative thresholds defined by the inverters Schmitt trigger. This circuit is often drawn using an opamp with positive feedback.

    Instead of using an inverter I chose to implement the oscillator with a NAND gate (I tend to use NAND gates because they are much more configurable, and therefore handy in my parts bin). So long as the NAND gate includes Schmitt trigger inputs the circuit should work the same. A NAND gate with one input tied to VCC is just an inverter after all 😉. Filtering by Schmitt trigger on Digikey led me to the Nexperia, 74ALVC00,118 who’s front page touts “Schmitt trigger action on all inputs makes the device tolerant of slow rise and fall times.” (This was my first mistake! Never trust the front page of a datasheet! D'oh!)

    The circuit I implemented is shown below, and does not work using the 74ALVC00. Instead, I found that clka_fb and clka_inv were locked around 1.65Vdc. I deliberately shorted C9 a couple times hoping to excite some sort of oscillation but the circuit would not oscillate. The DC value on clka_fb and clka_inv would vary somewhat between 1.6Vdc to 1.85Vdc (different after each startup).

    Determined to learn more I isolated one of the gates and started testing. I connected my function generator to “IN” and monitored both “IN” and “OUT” with my oscilloscope while the other input was connected to VCC.

    A slow upward ramp revealed some interesting behaviour. It wasn’t causing multiple triggers but it was terribly distorted when changing between Vin-low and Vin-high (or vice versa).

    In the next example I’m ramping IN close to the logic threshold then back down. My digital chip is acting more analog than I would like…

    Imagine Vcap is charged to 1.8V and causes the output to start decreasing. We can see in some of the screenshots above the output will hold around mid-rail so long as the input is similarly in the undefined region. As a result, both the capacitor as well as the output lock up at some DC voltage. We can prove this just by slowly stepping the DC voltage on IN.

    In this example, IN was slowly reduced until OUT was equivalent. At this point you can imagine no current will be flowing into or out of the RC timer and the circuit essentially holds its current state.

    Revisiting the datasheet for this part (and looking beyond the front page!!!). I noticed there’s a maximum input transition rise and fall rate. I am clearly violating this 10ns/V maximum rate. Another canary in the coal mine here is how the manufacturer specified the logic levels. For a Schmitt trigger input I’m used to seeing the logic levels communicated as positive-going threshold (Vt+), and for the hysteresis to be included.

    Resolution

    • Beware Schmitt trigger action != Schmitt trigger inputs (beware front page of datasheet!)
    • 74ALVC00 makes a piss poor relaxation oscillator (I’ll be using Nexperia, 74HC_132 instead)