Tatung Einstein Silicon Disc analysis

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IC1 LS273
IC2 PAL14L4 (i/o address decoder)
IC3 PAL14L4 (DRAM control signals)
IC4 LS374
IC5 LS244
IC6 LS04
IC7 LS245
IC8-15 41256 DRAM
R1  680R 
R2 1k
C1 47p
C2 47p
C3-10 47n ceramic caps for decoupling the DRAM chips

Only the PAL14L4 chips are hard to find, but they can be easily read and reverse-engineered for modern GAL16V8 chips.

The Gerber files have been obtained by some Einstein enthusiasts, and they are yet to make them public. Having the Gerbers, they do not need the circuit diagram to create new boards. All they need to do is send me the PALs for reading, and I can send them GAL16V8 chips to confirm they work.

I found the GAL equations here:

https://mikesretrotech.co.uk/userfiles/tatung%20einstein/hardware/Potential%20Projects/CF%20_%20SD%20Card%20Interface/Silicon%20Disc/Sdgal1.txt

and here:

https://mikesretrotech.co.uk/userfiles/tatung%20einstein/hardware/Potential%20Projects/CF%20_%20SD%20Card%20Interface/Silicon%20Disc/Sdgal2.txt

The designer has used the convention of having the active levels embedded in the equation. This then describes the logic level on named pins, instead of the true logic. This makes the logic harder to understand, and if you have to change a pin's active level then you have to change it in all the equations. If you have the logic level defined in the pin list, you only have to change it there, once. And the pin names match the names of the signals on the circuit diagram!

I've edited the equations to define the active levels in the pin lists, and added explanatory comments for my own benefit (and hopefully other people).

I have compared my reproduced logic chips with the original chip behaviour, and they match.