With the hardware design revision 1 complete and the usual amount of doubting my design choices it's time to get it made when both finances and time permits. 

For clarity going forward I will call ports P0.1 to P0.7 the columns and P1.0 to P1.7 and P2.0 to 2.5 the rows, I can see myself getting confused.

I have chosen to use 74HC138 chips to pull the rows low and a 74HC165 to read in the columns which will be pulled high via 10K resistors. Using a running/walking zeros method each row will be pulled low in turn and then the columns will be read. If a column input is low then a key had been pressed.

Issues I will likely come up against.

1. Switch de-bounce - mechanical key switches are noisy each having a mechanical make-break episode when pressed

2. Typematic delay - giving the keyboard the ability to fill any document with the same key press when you accidentally leave a book resting on the space bar.

3. Bi-directional communications - PC keyboards have LEDs that the BIOS or operating system turn on and off when you press certain keys. The keyboard doesn't have LEDs so the bi-directional communications bit it up for further thought.

4. Scan codes - keyboards don't send ASCII characters they send scan codes that's why you can select different languages and types. They also send key release data packets so you can do the old CTL-ALT-DEL. Each key will have a scan code sent out when the key is pressed and a release code when you lift you finger followed by the scan code for the key released. 

5. Other - The data sent by the keyboard also has a parity bit so this will need to be calculated prior to being sent.

One final note sort of a inference from observation. P3.2 on the 8051 IC is an interrupt. The clock line between keyboard and host is pulled low by the host to send commands to the keyboard so having that line connected to and interrupt would be helpful.