The 7 wires should be organised and ordered to reduce EMI and crosstalk.

I expect the wires to lie in parallel on a PCB, usually over a ground plane and/or interleaved with parallel ground traces

D0 g D1 D2 g D3 D4 g A B

• D0 is at the exterior and is likely to be "most active" as it would transmit the often-changing Inversion bit. But the inversion operates on a 10-bit pair so it gets paired with a half-changing bit.
• Clock signals A and B are usually transitioning 2× per 4-cycle data transaction, so it's almost guaranteed that only one transition per data transaction occurs, reducing the need for immediate grounding. Of course more grounding or pairing is good, but we're talking about minimal requirements here and the clock wires are somehow shielded from the two neighbour data wires D3 / D4.

Pins can be renumbered, such as

A B g D0 D1 g D2 D3 g D4

and the inversion bit would be D4. But this shows the influence of data transition statistics over the circuit's geometry, and one data bit is not "like the others" and would be placed apart.