My goal for this project is to build a (somewhat) general purpose data acquisition device that's capable of digitising two analog inputs and streaming the resulting samples to a PC over USB.

I now have a basic first-pass of this working. The main limitation at the moment is that it only streams a single channel.

On the hardware side I'm using a FT232H USB bridge and a Lattice iCE40 FPGA. The FT232H makes it easy to talk USB, while the FPGA interfaces between the USB bridge and the ADC.

Here's a picture of the set-up:

The ADC I'm using has a resolution of 10 bits and I'm running it at 8 MHz. If I use two bytes per sample, then for two channels, I'll need to push 32 MB/s over USB. To achieve this with the FT232H it must be configured in synchronous FIFO mode. In this mode, the FT232H generates its own 60 MHz clock to pace data transfers.

Since the FPGA sits between the ADC, which is driven by an 8 MHz clock, and the FT232H, which is driven by its internal 60 MHz clock, it has to handle cross domain clocking. The standard way to achieve this is with an asynchronous FIFO, and for that I'm using this library.

On the PC side, I'm using libFTDI to talk to the FT232H. I've written a very simple program to forward data from the device to stdout. The output from this can then be redirected to a file, or piped to another program for processing, visualisation, etc. The implementation is more-or-less just a thin wrapper around ftdi_readstream.

Here's a plot showing data captured using this set-up. In this example the input was driven by my LiteVNA in CW mode at 500 kHz.