This project is currently in the breadboard stage, because I haven't figured out the PCB portion of KiCAD.

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The Steering CMTE is an interface to provide Turbo Z80 power to any of the old Z80-based TRS-80s:

     Model I                              Model 4 (ga)                  Model II

     Model III                            Model 4P (ga)                Model 12

     Model 4 (nga)                   Model 4D (ga)                Model 16

     Model 4P (nga)                                                         Model 6000

As there are dozens of people working on fast retro Z80 computer projects, I did not see the point of re-inventing the wheel.  What I found was, however, that most lacked any external interface that would allow a plug-and-play experience with a TRS-80.

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The most approachable one to date is the Dino Boards Stegosaur (Green) Turbo Z80 Board by Dean Netherton of Australia. His design, made for the MSX operating system on the RC2014 extended 80-pin bus, already incorporates clock step-up/step-down logic that allows it to function in multiple environments.

As designed, he incorporated a 20MHz crystal to power a 20 MHz CMOS Z80. His Yellow version of the same board, included a 16MHz crystal as well to slow it down, in case you don't trust that speed. He provides that same crystal with the Stegosaur version on request. His board has three (3) switch-selectable speed settings: SLOWCLOCK, which uses the clock speed on the RC2014 bus, and is used for I/O space accesses, FASTCLOCK at crystal speed with 3 Wait States for memory, and FASTCLOCK at crystal speed with 1 Wait State for modern fast memory.

Any Turbo-mode Z80 used in a TRS-80 must deal with, not only slow I/O, like normal computers, but slow ROMs , slow memory-mapped keyboards, slow memory-mapped video displays, slow memory-mapped interrupt latches, slow memory-mapped disk select latches, slow memory-mapped cassette select latches, slow bidirectional memory-mapped printer ports, and slow memory-mapped disk controllers. It also has to deal with the timing of tight timing loops and programmed (as opposed to interrupt-driven) I/O. These all require the same clock step-down logic used by the I/O, and are the headaches of the two fundamental TRS-80 memory maps.

In addition to those timing considerations, all TRS-80s use "dynamic RAMs", that make use of the Z80 "hidden refresh" feature. It is not really documented anywhere, but virtually all 1-bit wide (4K/16K/64K/256K/1M) dynamic RAMs (except the the fastest <90ns access) require a minimum 110ns RFSH  signal  (up to 300ns RAMs) to maintain data integrity, no matter what the data sheets say. At 20MHz, the <2 T-State RFSH signal is <100ns, so I chose the 16MHz crystal, to guarantee a 120ns (<134ns) RFSH signal. 

Further, even though all RC2014 bus signals are active on the Turbo Z80 Board, The TRS-80 claims the entirety of the 64K Z80 memory space: all RC2014 I/O is available to access by the TRS-80 (watch out for port conflicts), but any RC2014 memory is guaranteed to cause bus contention with the TRS-80, unless the memory address is unpopulated on the TRS-80 bus. The only exception I can think of is the use of the RC2014 eZ80 coprocessor board using its own memory, acting as bus master to access the TRS-80 memory. It will still have a problem with slow memory-mapped I/O, though.

I had to make some minor alterations to the Dino Boards Turbo...