A 30-Year-Old Guitar Amp Circuit Stores Neural Network Weights
— DTL Ternary Cell, Public Domain

The same DTL circuit I designed in the 1990s for 3-channel tube amplifier
footswitching is a ternary memory cell storing {-1, 0, +1} neural network
weights — one transistor per weight, no clock, no refresh, 30 years of
production hardware behind it.

I designed this circuit in the 1990s for a 3-channel tube amplifier.
Channel A. Channel B. Channel C. One button selects any channel directly
from any other — one press, no intermediate off state. One green LED on
at all times. The switching is instant, clean, and glitch-free inside a
100-watt tube amp chassis — one of the most electrically hostile
environments you can put a low-level switching circuit into.

I have built 3-way, 4-way, and 6-way versions. All in production. All
deployed in real amplifiers.

In 2026 I recognized it as something else.

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WHAT THE CIRCUIT IS
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Three positions. One transistor always conducting. The switching is done
by the diode array operating on unbalanced contact potential — not by the
transistors. The transistors are output stages. The diodes make the
decision.

Each position: B+ through a pull-up resistor to a node. From that node:
one diode to its own transistor base, and diode connections to all other
positions' collectors.

When position 1 is active (transistor conducting, collector LOW):

  Active collector LOW + one diode drop  =  ~0.8V at positions 2 and 3
  Two diode drops required to drive base  =  ~1.2V minimum threshold
  0.8V < 1.2V — positions 2 and 3 cannot conduct

The two inactive collectors are HIGH. Those two HIGH collectors feed
current through their diodes back to position 1's base — sustaining it
above threshold. Position 1 holds indefinitely. No clock. No stored
charge. No capacitor. No external hold signal.

One transistor always conducts. One current path: B+ → R → collector → GND.
The designer sets R. The designer sets the margin. The gap between 0.8V
and 1.2V is the hold. Supply voltage controls immunity.

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WHY IT IS TERNARY
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Three stable states. One always active. Position is meaning.

  Position 1 active  =  {-1}   negative weight
  Position 2 active  =  {0}    zero weight
  Position 3 active  =  {+1}   positive weight

This is exactly the ternary quantization scheme used in ternary neural
network inference — including Microsoft's BitNet b1.58 and related
architectures. Every weight in a ternary-quantized model is one of
{-1, 0, +1}. One DTL cell stores exactly one weight. One transistor.
No binary encoding. No decode. Position is the value.

Compare to binary SRAM:
  SRAM stores one weight value in 7-8 flip-flops = 42-48 transistors.
  DTL ternary stores the same value in 1 transistor.
  No clock. No refresh. No forbidden state.

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N-ARY BY NATURE
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The circuit does not have a preferred base. The diode contact potential
mechanism works identically for any N.

  N=2:    binary flip-flop. No clock. No forbidden state.
  N=3:    ternary trit. {-1, 0, +1}. One transistor per neural weight.
  N=4:    ternary plus idle. Position 4 = weight not loaded.
  N=6:    six-position selector. Built and deployed in hardware.
  N=18:   LTSpice verified (CYR_OneHot_18way_v3.cir).
  N=128:  one-hot ASCII storage. Full character set. One transistor per
          character. Detailed in the previous Hackaday release:
          "One LOW in 128 HIGH Lines."

Same topology. Same contact potential mechanism. Same single transistor
per stored value. Any base. No redesign required.

If your ternary application needs an idle or NULL state — use N=4.
Position 4 is off by convention. Already proven in the 6-way hardware.

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PRODUCTION EVIDENCE
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This is not a proposed design. This is a 30-year-old production circuit.

3-way versions: deployed in 3-channel tube amplifiers since the 1990s.
  Channel switching under live signal. 100-watt output stages. High-
  voltage transformer transients. 60Hz chassis fields. Works reliably.

4-way and 6-way: also built and deployed. All versions in production use.

The perfboard demo boards pictured were built to demonstrate function
to patent counsel (Irell & Manella LLP, 2026). The circuit needs no
explanation — one LED on at a time, press a button, that LED turns on,
the previous one turns off. Instantly. Every time.

The 3-way 4-mode footswitch (separate circuit, more complex):
  A, B, C channel selection plus explicit off.
  Off is achieved by pressing the active channel's button.
  The cap-stored trigger mechanism enables the 4th mode.
  This is NOT the basic ternary cell — it is a production footswitch
  application with additional functionality built on the same primitive.

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SIMULATION EVIDENCE
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6-way and 18-way versions verified in LTSpice (CYR_OneHot_18way_v3.cir).
Sequential LOW pulses. One active position at all times. All others held
off by the diode contact potential network. Identical behavior at any N.

A 3-way simulation is a strict subset of both. The result is not in
doubt — 30 years of hardware already proved it.

Verilog RTL: cyr_onehot_storage.v (parameterized, N=128 default).
For ternary: parameter N = 3. That is the complete change.
Public domain. Available on the ASCII project page.

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PRIOR ART TIMELINE
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1990s       Original 3-way circuit designed for 3-channel tube amplifier.
            4-way and 6-way versions also built and deployed.

Feb 2022    Public disclosure, diyAudio forum, Wolf13:
            "The switching is done at the diodes. Expandable to 3-way,
            6-way, whatever you like. Unbalanced contact potential."
            Currently #1 on Google: "dtl flip flop circuit diagram."

2026        Working hardware demonstrated to patent counsel.
            Reduction to practice formally witnessed.

Aug 2026    Hackaday: "One LOW in 128 HIGH Lines" — ASCII release.
            6-panel JPG package, 6-way schematic, LTSpice 18-way,
            Verilog N=128. Public domain.

Aug 2026    This post: ternary application documented. N=3.
            Prior art on ternary neural network weight storage.

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ERROR IMMUNITY IN PRODUCTION
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Thirty years in tube amplifier chassis is the noise immunity test.
Motor drives, output transformer leakage, high-voltage switching,
60Hz fields — the circuit holds state through all of it.

The mechanism explains why: inactive nodes sit at ~0.8V. The threshold
to drive an inactive base is ~1.2V. That 0.4V gap is the immunity margin.
The active transistor's collector is always sinking current — actively
suppressing any upset in real time. Passive charge deposits from EMI
or radiation cannot sustain current against an active low-impedance sink.

Thirty years of tube amps proved the principle. LTSpice confirmed it.
Physics explains it.

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PUBLIC DOMAIN DECLARATION
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Alan Cyr (Wolf13), CYR Technologies, Chicago, releases the DTL ternary
cell and all N-way variations to the public domain, August 2026.

Free to use. Free to build. Free to sell. Free to patent improvements.
No license. No royalty. No attribution required.

The circuit itself predates any patent filing. It is prior art from the
1990s. Anyone may build it. The application to ternary neural network
weight storage is documented here as prior art, August 2026.

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FILES TO UPLOAD WITH THIS POST
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  3way4mode.dsn          3-way 4-mode footswitch schematic (production)
  cyr_onehot_storage.v   Verilog RTL — set parameter N=3 for ternary
  CYR_OneHot_18way_v3.cir  LTSpice 18-way netlist (N=3 is subset)

Images:
  Perfboard 3-way with 3 LEDs (production demo board)
  Perfboard 2-position flip-flop (single LED)
  3-way 4-mode schematic (Alan Cyr, G:\cad\3but4mode.dsn)

See also: "One LOW in 128 HIGH Lines" — the N=128 ASCII release.

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ternary, dtl, flip-flop, neural-network, memory, no-clock,
public-domain, discrete-components, guitar-amplifier, ai-hardware

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Wolf13 / Alan Cyr · CYR Technologies · Chicago · August 2026
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