Name: Pipelined 32-bit RISC-V (RV32IM) Processor

Architecture:
- IF: pc_reg, pc_adder, instr_mem, if_to_id_reg
- ID: control_unit, register_file, imm_gen, branch_unit, hazard_detection_unit,                        id_to_ex_reg
- EX: alu, alu_control, forwarding_unit, mul_div_unit, ex_to_mem_reg
- MEM: data_memory (4× SRAM), mem_to_wb_reg
- WB: wb_mux

-Features: full ALU A/B forwarding, 1-bubble load-use stall, early ID branch + flush, iterative MUL/DIV (mul/mulh/mulhu/div/divu/rem/remu), LB/LH/LBU/LHU/SB/SH/SW, JAL/JALR PC+4, 4× sky130_sram_1kbyte_1rw1r_8x1024_8 (4KB)

Tools: Icarus + GTKWave, Yosys, OpenRAM via sky130_sram_macros, OpenROAD (flow.tcl), Sky130A (fd_sc_hd + SRAM macros), Magic/KLayout.
Verification: tb/rv32im_top_tb.sv, 16/16 pass — R-type, I-type, loadstore, all branches, branch-after-ALU, load-use, RAW b2b/gap, JAL/JALR, LUI/AUIPC, MUL, DIV (div0/overflow), x0, factorial, fibonacci, mixed stress.

Physical: 1.5mm² (1250×1200µm), 62% util, 18,759 inst (4 SRAM, 8160 taps, 866 endcaps, 290 CTS), 457kµm wire, 10ns target, WNS −2.29ns / TNS −12.6ns (TT 25°C 1.8V), 0 DRC, LVS not run. Fix per README: 13ns or move branch ID→EX.

Run: iverilog -g2012 -o sim.out tb/rv32im_top_tb.sv rtl/**/*.v && vvp sim.out; yosys synth/sky130_synth.ys; openroad -no_init -exit flow.tcl.