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Rahul shah

ECE student building RISC-V processors, RTL & VLSI projects, turning ideas into silicon.

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This user joined on 07/07/2026.

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5-stage pipelined RV32IM CPU in Verilog: forwarding, M-extension, 16/16 tests pass, Yosys+OpenROAD Sky130 PnR.
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Pipelined RV32IM RISC-V Core RTL to GDS on Sky130

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