The DDR3 controller timed out in calibration on every attempt for two days: more power, the other SOM geometry, each x16 device on its own, external VREF, nothing moved it. Then Sipeed's own reference image passed on the same board, and the difference was the clock.

The board clock is 50 MHz, not the 27 MHz I had assumed, and Gowin derives the PLL's charge-pump and loop-filter settings from the declared input frequency string, so my hand-written PLL had never been right. Along the way the HDMI capture card was rejecting valid signals as blank frames, which cost a night chasing a lock failure that did not exist.

With the generated PLL restored, calibration passed, then every address line in the 1 GiB map, then a logo streamed continuously from DDR3.

Episode 3: The Tang Console's Memory Wasn't Broken. We Were.