OVERVIEW: one small station, many listeners

two-board setup

The AD9248 board (on the left) is the acquisition end: 

  • antenna input conditioning 
  • and high-speed conversion. 

https://www.analog.com/media/en/technical-documentation/data-sheets/ad9248.pdf


The SmartZynq SP2 (on the right) is the processing end: 

  • it receives the sample stream, 
  • runs the digital signal processing pipeline in programmable logic, 
  • provides the operating system and network interface.

http://www.hellofpga.com/index.php/2024/01/21/smart-zynq-sp2/

The firmware turns a single digitized RF high speed stream into a set of configurable receive channels. 

Each channel has its own digital oscillator, filter, decimator, and output stream. 

This makes the hardware reusable: choose the frequencies in configuration instead of rewiring a receiver.

The intended first-use flow is:

1. Flash the supplied SD-card image or firmware bundle.
2. Connect the ADC board to the SmartZynq SP2 and attach the antenna.
3. Connect power and Ethernet.
4. Select a preset—such as multi-band FT8, WSPR monitoring, or a custom channel plan.

### Channels are software, not hardware

![Conceptual multi-channel waterfall](assets/multichannel-monitoring.png)

The FPGA performs the repetitive high-rate work close to the ADC: digital down-conversion, filtering, and decimation. The processor side packages lower-rate IQ or audio streams for a local decoder, a network client, or logging software.

Example channel plans:

| Preset           | Example allocation                                                                                |
| FT8 watcher | One receive slice per selected amateur band                                       |

| WSPR beacon monitor | Persistent WSPR slices plus spare experimental channels |
| Mixed digital bench | FT8, WSPR, CW/skimmer, and a general-purpose IQ stream |

Actual simultaneous channel count, usable coverage, and dynamic range will be documented from measured firmware builds. 

Input filtering and antenna protection remain important, especially with strong nearby transmitters.


Why these two boards?

The AD9248 provides fast dual-channel conversion, while the SmartZynq SP2 pairs FPGA fabric—ideal for many parallel DDCs—with an embedded processor that can boot, configure the receiver, and serve results over Ethernet. Together they move the difficult hardware work into a repeatable two-board assembly and leave experimentation to firmware.


Block diagram

The antenna enters the ADC board, where it is protected, filtered, and matched before conversion. 

Sample data crosses to the SmartZynq SP2, whose FPGA creates independent digital channels. 

The SoC then exposes those channels as IQ, audio, or decoded/spot data over the network.

Project status

Architecture and project presentation are in place. 

Next milestones: 

  • validate the ADC interface, 
  • publish a repeatable firmware image, 
  • characterize RF performance, 
  • release channel presets 
  • setup documentation.