FelipeSBonetto
Running on the FPGA
The README demo shows LFM2.5-230M running in otpu-chat, alongside otpu-smi monitoring utilization and DRAM bandwidth.
The hardware
The YPCB-00338 board provides 4 GiB of DDR3 across two 2 GiB channels and connects to the host over PCIe Gen2 x8. Its board build combines a four-column systolic matrix unit, eight vector lanes, and LiteDRAM memory controllers. The repository documents building the bitstream, programming the FPGA, and checking the card with host diagnostics.
Inside the accelerator
A sequencer coordinates matrix operations, vector arithmetic, quantization, and explicit memory transfers. The ISA defines the arithmetic and memory behavior shared by the compiler, simulator, and RTL, so each implementation can be checked against the same specification.
Explore the source code, board setup guide, and instruction set.
Yunsup Lee
Your Pal Kal