Published first version of my Verilog version of this project

A project log for TMS9900 compatible CPU core in VHDL

Retro challenge 2017/04 project to create a TMS9900 compatible CPU core. Again in a month... Failure could be an option...

Erik Piehl • 06/15/2020 at 20:10•1 Comment

If you are interested, I have created a Verilog version of the TI-99/4A. It can be synthesised with the open source IceStorm toolchain. Supports the cool ULX3S board.

Very much work in progress, but due to some interest I decided to release the code in its current version. Please see:

https://github.com/Speccery/icy99

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01/19/2019 at 09:35 • 0 comments

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zpekic wrote 06/15/2020 at 21:48

Awesome!!! I have a plan (time permitting...) to write a TMS9900 core using my microcode compiler (after all, the original was microcoded too) and I will use this as a reference!

Btw, the 16 regs are actually implemented "on chip" as dual port cache memory?

Are you sure? yes | no

Published first version of my Verilog version of this project

Added cache

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