My current working design uses a buffer gate for each bit of data. A capacitor connects to the input of the buffer. A diode goes from the output of an AND gate to the capacitor, positive lead to the AND. The AND's inputs connect to the output of the bit's buffer gate and to the refresh clock. For the buffer I used 2 NOT gates, which works well. Im going to create an array of maybe 4 bytes for test. Here is an image of what I have so far: