Dylan BrophyMy 74173s came in the mail today. Tested and working, so I came up now with a plan to make everything and I have a preliminary design. First a picture of my new parts:
This is basically where I tested and my current setup. Don't worry, I have plenty more breadboards. Anyways, I'll show my preliminary schematic, then my plan for completing this project that would be otherwise a bit too complex for me to handle. My schematic:
Essentially the slice has 4 registers: A, B, C, and PC. In the instruction they can be disabled, to access IO. The IO address could be formulated from bits 3-6 of the instruction. I still need a way to access IO and registers in the same instruction, and add RAM access. But I want to keep the instruction width 8 bits! I will probably impliment a more complex state machine later. Also, take note of the logic that processes the first 3 bits of the instruction. Kudos to @agb.cooper for coming up with that logic. See his project #The 74LS181 ALU for a better schematic. It's basically to lessen the # of bits needed in the instruction. The idea is to remove ALU functions you don't need in exchange for more instruction bits (At least in my case). So yes, lots to improve.
My plan is to make the Slice in sections on breadboards to make sure everything works, then as each part is finalized solder it onto the PCB. I'll start with a registers section. What other sections should I break it up into? ALU, random logic...? We shall see!
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Hi Dylan,
I can't really see the benefit of a separate programming and random access memory. It has a simpler control logic but then the CPU is not programmable stand alone. Not very "cool".
The following rationale is wrong:
"This strange architecture allows for all slices to receive the same instructions but it makes the design exceedingly difficult."
The opcode decoder cannot be bit sliced (that is I don't know how to bit-slice it). You have a single decoder board that send signals to the bit slice boards. You don't have a decoder on every bit-slice board. You can bit slice the PC, the registers, the comparator, the ALU functions and the I/O. The rest (Timing/Decoder/PROM/RAM) you cannot bit slice.
If bit-slicing is your primary goal (and it is a magical approach!) then you REALLY have to modify your approach to SUIT bit slicing. With a very very minimalistic bit slicing you have:
* A decoder/timing board
* An address space decoder and/or prom/memory board
* A bus (this is not as easy as it seems)
* Bit-slice boards (you can even include the front panel or I/O here)
Part of the magic of bit slice is that the step down to a transistors CPU is just detail!
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Regards AlanX
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Hi Dylan,
Have a look at my Weird CPU which is very very minimal. Its 8 bit data/address and I have worked on a bit-slice version (but unfinished). After that have a look at my 4 bit CPU (in progress). You may find some practical ideas for your CPU.
Rather than use bread board I would suggest strip-board as debugging a CPU is an absolute nightmare and unreliable connections may beat you up more than you can manage. I used DIY-LC to design the strip-board (free) - there is only so far you can get with pencil and paper (been there!).
I would suggest mapping I/O to memory space as it is easier.
Most of the work associated with discrete minimalist CPU is with the timing and/or instruction decoder. After that design your "bus". Once you get that sorted the PC, ALU, RAM/ROM and I/O is rather simple.
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OpCodes
========
Assuming you are basically 8 bit, the idea of merging the OpCodes and the Address space is a bit of a trap. Just use the first byte fetch for the OpCodes (you don't have to use all 256 values!) and subsequent fetches/deposits as addresses or data. For a very simple CPU the timing would be:
[Fetch OpCode][Fetch Address][Deposit Address]
You could then add this format:
[Fetch OpCode][Fetch Immediate Data][Deposit Address]
This OpCode style is for an Accumulator only CPU. The Weird CPU format is even simpler:
[Ftech Address][Deposit Address]
If you want a register style CPU then:
[Fetch OpCode | Register][Fetch Address]
[Fetch OpCode | Register][Deposit Address]
[Fetch OpCode | Register][Data]
The fun start when you look at the signals, the temporary registers and getting the PC to "jump".
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The breaking up of a CPU into sections
==================================
Break it up a small as possible that allows you to test the function:
* Timing/Decoder
* Program Counter
* Registers
* PROM/RAM
* Input/Output (front panel)
* ALU:
- Comparator
- ALU
For the Weird CPU I had:
* TIMING
* PROGRAM COUNTER
* ADDER
* NAND
* COMPARATOR
* PROM/RAM
* FRONT PANEL (IO)
Regards AlanX
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Wow, thank you for your very insightful and well - written comment. I have read it and I have some thoughts.
It will be a register style CPU, and use the associated opcode style.
I want to have 4 registers, one of which being the PC. Essentially the
PC would act like a normal register but just increment for the next
byte.
I will use your advice on NOT breadboarding. I found that soldering together a not-working breadboarded Z80 computer to a PCB actually made it work. Ironic.
The hard part about my SBP CPU is that it would have 2 memory spaces:
Instruction RAM and long RAM. Long RAM is distributed between slices.
This strange architecture allows for all slices to receive the same instructions but it makes the design exceedingly difficult.
Maybe I could just grab the instructions from "Long RAM" and do away with this dual-memory-space crap?
No matter what I need the slices to send addresses between slices too... I guess I still have a lot to think about. I will make a new design, as I was going to, but incorporate your ideas and these ideas.
I will use your projects and your amazing comment for reference. Actually, I should probably print it out. Too bad I don’t have a printer....
Thank you,
~Dylan
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