I've started assembling the first part of my clock circuit. I decided to partly follow the steps of Ben Eater.

I'll have a variable clock using a LM555, then a push button to step one instruction debounced with an LM555, and then a push button to select between the two debounced with an LM555.

However, I'm departing a bit after that. He has a HALT command to stop the clock until a reset is performed. I think it's more useful to have a BREAK command to stop the clock. The clock can still be manually stepped if the BREAK line is high. This allows you to step past the BREAK command and continue operation. So this can be used as a debug function instead of just stopping the processor until reset. I worked out the digital logic and it looks something like this:

I decided to use two TTL OR gates, and then a wired-AND and a transistor inverter. I chose the OR gate chip because the clock is going to have a large fan-out, so I want a good driver. I could have done the same thing with another chip or two, but this should be more compact. The pull-up style logic will be slower than a TTL gate, but I'll have to check to see how slowly. Eventually I may tap into the UART chip's crystal to provide my clock, at which point I'll want to replace the wired-AND with a real TTL chip. I may be able to pull it off with a single NAND or NOR.

I wanted to add one more thing: this is a bad way to design a clock circuit. There can still be glitches when switching between clock domains. If the clock pulses high, then the select line immediately switches to the step mode, there can be a timing violation in the flip-flops (clock too-short). So some flip-flops will switch state and some will not. I haven't fixed it, but I may later.