Although monitoring the lower 16 bit of the address line should be possible by using only the two 8-bit ports PORTC and PORTL of an ATmega2560 and triggering an interrupt with the WRITE-signal, the RAM frequency of around 3MHz is a bit too high to get reliable address-readouts because of the sequential readout (8-bit uC -> 2 8-bit readings of a 16-bit bus).
Therefore, a CPLD will be added to the parts list, which will do the address monitoring until a better implementation has come to my mind.
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