So Falstad is a reasonably potent logic simulator that lets me input schematics easily and test them.

I had hit a bug in the ALU8's CLA when porting the #VHDL library for gate-level verification back to #YGREC8 and went to other sides of the project, because I didn't feel the energy to go back through all the optimisations I made. But thanks to Falstad I can do it interactively...

So I went back to the main diagram and rebuilt the whole thing in Falstad's simulator:

The source code is so large I can't add it as a link so it's in the file Add8.cjs.

Slowly, little by little, I can resume the "bubble pushing" that created the nasty bug, but this time I can avoid it :-)