The state of the YGREC8 core is represented by the A1, A2, R1, R2, R3 and PC registers, as well as the three Status flags C, S and Z. Of course, this excludes the memories (instructions and data) as well as all the I/O space registers (some could store bank numbers) but here I focus on the core.

The three flags take three bits and that fits in a byte, with 5 bits left. With the new PF opcode, this free space is now totally used:

• One bit is set when the current opcode of PF. This will be cleared by the next instruction, which will start by looking at this flag to modify its behaviour.
• One bit will be new carry input, selected during the PF cycle by the condition field.
• Three bits contain the real destination of the next instruction.

1+1+3+the existing flags equals 8, it fits nicely.

This matters not only for the simulator, but also because the core needs to handle interrupts and traps, which requires an accurate snapshot of the core that allows a precise restart.

There are some unused fields in the PF instructions, which might require more bytes to be stored for the next instruction.