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A project log for Field oriented control motor control on FPGAs

Will is spin or smoke? Stay tuned!

adam-langeAdam Lange 11/22/2017 at 05:461 Comment

I'm implementing logic that takes as an input a voltage vector in space vector space, and outputs values that the pwm timers use to generate the inverter gate drive logic.  I'm using Vivado-HLS to do this.  I've written some code, C code!  Eventually Vivado-HLS will turn that code into Verilog, but the first step is to create a test that runs on-laptop to verify that the C code to be transformed actually behaves the way it should before synthesizing Verilog from C.  Here's the current output from the test:

When this is working as it should, it will look like three sinusoids spaced with 120 degree phase angle, not like three winking skeletons.

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rubypanther wrote 11/22/2017 at 06:41 point

It looks more like dancing bunnies to me.

Looks like a couple offsets and a multiply and you'll be there. 3 bugs, maybe 4.

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